Timer Status Register (Tsr) - Renesas F-ZTAT H8 Series Hardware Manual

10.2.12 Timer Status Register (TSR)

TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel Abbreviation
0 TSR0
1 TSR1
2 TSR2
3 TSR3
4 TSR4
Bit 7
—
Initial value 1
Read/Write —
Note: Only 0 can be written, to clear the flag.
*
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in TIER.
TSR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Function
Indicates input capture, compare match, and overflow status
6 5 4
— — —
1 1 1
— — —
Reserved bits
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Section 10 16-Bit Integrated Timer Unit (ITU)
3 2
— OVF
1 0
— R/(W) *
Overflow flag
Status flag indicating
overflow or underflow
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Rev. 7.00 Sep 21, 2005 page 345 of 878
1 0
IMFB IMFA
0 0
R/(W) * R/(W) *
REJ09B0259-0700