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11.2.7
Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP
to TP
) on a bit-by-bit basis.
7
0
Bit
7
NDER7
Initial value
0
Read/Write
R/W
If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected in
the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to
the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is
not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP
Bits 7 to 0:
NDER7 to NDER0
0
1
Section 11 Programmable Timing Pattern Controller
6
5
NDER6
NDER5
NDER4
0
0
R/W
R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
to TP
) on a bit-by-bit basis.
7
0
Description
TPC outputs TP
to TP
7
(NDR7 to NDR0 are not transferred to PA
TPC outputs TP
to TP
7
(NDR7 to NDR0 are transferred to PA
4
3
2
NDER3
NDER2
0
0
0
R/W
R/W
R/W
are disabled
0
to PA
7
are enabled
0
to PA
7
Rev. 3.00 Mar 21, 2006 page 407 of 814
1
0
NDER1
NDER0
0
0
R/W
R/W
(Initial value)
)
0
)
0
REJ09B0302-0300
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