Fsi Byte Count Register (Fsibnr) - Renesas H8S/2100 Series Hardware Manual

21.3.3

FSI Byte Count Register (FSIBNR)

The FSIBNR sets the number of bytes to be transmitted or received by the FSI. This register
should not be set in the processing other than FSICMDI and FSIWI interrupt processing.
Bit Bit Name
7 to 4 TBN3
TBN2
TBN1
TBN0

3
R/W
Initial
Value EC Host Description

0 R/W
0
0
0

0 R/W
Transmit Byte Count 3-0
These bits specify the number of data bytes to be
transmitted. The TBN value is decremented each time
one byte of FSI data transmission is completed. When
the FSI transmission ends, TBN is cleared to B'0000.
0000: Transmits no data
0001: Transmits one byte of data
0010: Transmits two bytes of data
0011: Transmits three bytes of data
0100: Transmits four bytes of data
0101: Transmits five bytes of data
0110: Transmits six bytes of data
0111: Transmits seven bytes of data
1000: Transmits eight bytes of data
1001 to 1111: Setting prohibited
If transmission of nine bytes or more is specified, data
in FSITDR7 is transmitted.
Reserved
The initial value should not be modified.
Rev. 1.00 Apr. 28, 2008 Page 689 of 994
Section 21 FSI Interface
REJ09B0452-0100