Ata_Control; Ata_Status - Samsung S3C2451X User Manual

CF CONTROLLER
ATA_CONTROL REGISTER
Register

ATA_CONTROL

0x4B801900
ATA_CONTROL
Reserved [31:2]
clk_down_ready
ata_enable
ATA_STATUS REGISTER
Register

ATA_STATUS

0x4B801904
ATA_STATUS Bits
Reserved [31:6]
atadev_cblid
atadev_irq
atadev_iordy
atadev_dmareq
xfr_state [1:0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
8-16
Specifications and information herein are subject to change without notice.
Address R/W
R/W
Bits
Reserved bits
[1] Status for clock down
This bit is asserted in idle state when ATA_CONTROL bit
[0] is zero.
0 : not ready for clock down
1 : ready for clock down
[0] ATA enable
0 : ATA is disabled and preparation for clock down
maybe in progress
1 : ATA is enabled.
Address R/W
R ATA Status register
Reserved bits
[5] ATA cable identification
[4] ATA interrupt signal line
[3] ATA iordy signal line
[2] ATA dmareq signal line
Transfer state
2'b00 : idle state
2'b01 : transfer state
2'b11 : wait for completion state
Description
ATA Control register
Description
Description
Description
S3C2451X RISC MICROPROCESSOR
Reset Value
0x0000_0002
R/W Reset Value
R
R
R/W
Reset Value
0x0000_0000
R/W Reset Value
R
R
R
R
R
R
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0