Figure 21.5 External Clock Input Timing; Figure 21.6 Timing Of Output Stabilization Delay Time For External Clock; Table 21.4 Output Stabilization Delay Time For External Clock - Renesas H8S/2437 Hardware Manual

EXTAL
When a specified clock signal is input to the EXTAL pin, internal clock signal output is
determined after the external clock output stabilization delay time (t
signal output is not determined during the t
in the reset state. Table 21.4 shows the output stabilization delay time for the external clock.
Figure 21.6 shows the timing of the output stabilization delay time for the external clock.

Table 21.4 Output Stabilization Delay Time for External Clock

Condition: V = 2.7 V to 3.6 V, AV
CC
Item
Output stabilization delay time for
external clock
includes a RES pulse width (t
Note: * t
DEXT
2.7 V
V
CC
V
IH
EXTAL
φ
(Internal and external)
Note: * t includes a
DEXT

Figure 21.6 Timing of Output Stabilization Delay Time for External Clock

Rev. 1.00, 09/03, page 616 of 704
t
EXH
t
EXr

Figure 21.5 External Clock Input Timing

DEXT
= 2.7 V to 3.6 V, V
CC
Symbol
t *
DEXT
RESW
t
DEXT
pulse width (t ).
RESW
t
EXL
t
EXf
DEXT
cycle, a reset signal should be set to low to hold it
= AV = 0 V
SS SS
Min. Max.

500
).
*
V × 0.5
CC
) has passed. As the clock
Unit Remarks
µs
Figure 21.6