Figure 19.5 External Clock Input Timing; Table 19.3 External Clock Input Conditions; Table 19.4 External Clock Output Stabilization Delay Time - Renesas H8S/2111B Hardware Manual

Table 19.3 External Clock Input Conditions

Item
External clock input pulse
width low level
External clock input pulse
width high level
External clock rising time
External clock falling time
Clock pulse width low level t
Clock pulse width high
level
EXTAL
The oscillator and duty correction circuit have a function to adjust the waveform of the external
clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL
pin, internal clock signal output is determined after the external clock output stabilization delay
time (t ) has passed. As the clock signal output is not determined during the t
DEXT
signal should be set to low to hold it in reset state. Table 19.4 shows the external clock output
stabilization delay time. Figure 19.6 shows the timing of the external clock output stabilization
delay time.

Table 19.4 External Clock Output Stabilization Delay Time

Condition: V = 3.0 V to 3.6 V, V
CC
Item
External clock output stabilization delay
time
includes a RES pulse width (t
Note: * t
DEXT
Rev. 1.00, 05/04, page 458 of 544
V
CC
Symbol Min
t 40
EXL
t 40
EXH
t —
EXr
t —
EXf
0.4
CL
80
t 0.4
CH
80
t
EXH
t
EXr

Figure 19.5 External Clock Input Timing

= 0 V
SS
Symbol
t
DEXT
RESW
=3.0 to 3.6 V
Max Unit
— ns
— ns
10 ns
10 ns
0.6 t
cyc
— ns
0.6 t
cyc
— ns
t
EXL
t
EXf
Min. Max.
500 —
*
).
Test Conditions
Figure 19.5
φ ≥ 5 MHz
Figure 22.5
φ < 5 MHz
φ ≥ 5 MHz
φ < 5 MHz
V × 0.5
CC
cycle, a reset
DEXT
Unit Remarks
µs
Figure 19.6