Pll Circuit; Figure 21.5 External Clock Input Timing; Table 21.3 External Clock Input Conditions - Renesas H8S/2368 Series Hardware Manual

Table 21.3 External Clock Input Conditions

Item
External clock input
low pulse width
External clock input
high pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
EXTAL
21.3

PLL Circuit

The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 1, 2, or 4. The multiplication factor is set with the STC1 and the STC0 bits in PLLCR.
The phase of the rising edge of the internal clock is controlled so as to match that of the rising
edge of the EXTAL pin.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0, the setting becomes valid after a transition to software standby mode. The
transition time count is performed in accordance with the setting of bits STS3 to STS0 in SBYCR.
For details on SBYCR, refer to section 22.1.1, Standby Control Register (SBYCR).
1. The initial PLL circuit multiplication factor is 1.
2. A value is set in bits STS3 to STS0 to give the specified transition time.
Rev. 2.00, 05/03, page 680 of 820
V
to 3.6 V
Symbol Min
t 15
EXL
t 15
EXH
t —
EXr
t —
EXf
t 0.4
CL
t 0.4
CH
t
EXH
t
EXr

Figure 21.5 External Clock Input Timing

= 3.0 V
CC
Max Unit
— ns
— ns
5 ns
5 ns
0.6 t
0.6 t
t
EXL
t
EXf
Test
Conditions
Figure 21.5
cyc
cyc
× 0.5
V
CC