Multiprocessor Serial Data Reception - Renesas H8 Series Hardware Manual

Section 14 Serial Communication Interface 3 (SCI3)
14.6.2

Multiprocessor Serial Data Reception

Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving
data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request
is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure
14.18 shows an example of SCI3 operation for multiprocessor format reception.
Rev. 1.00 Aug. 28, 2006 Page 234 of 400
REJ09B0268-0100