Figure 11.2 Watchdog Timer Mode (Rst/Nmi = 1) Operation - Renesas H8S/2111B Hardware Manual

H'FF
H'00
RESO signal
Internal reset signal
[Legend]
WT/IT:
TME:
OVF:
Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset.
The XRST bit is also cleared to 0.

Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation

Rev. 1.00, 05/04, page 228 of 544
TCNT value
WT/IT = 1 Write H'00 to
TME = 1 TCNT
Timer mode select bit
Timer enable bit
Overflow flag
Overflow
WT/IT = 1
OVF = 1*
TME = 1
RESO and internal
reset signals generated
132 system clocks
518 system clocks
Time
Write H'00 to
TCNT