Operation; Watchdog Timer Mode; Figure 11.2 Operation In Watchdog Timer Mode - Renesas H8SX/1500 Series Hardware Manual

Section 11 Watchdog Timer (WDT)
11.3

Operation

11.3.1

Watchdog Timer Mode

To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1.
When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1.
When the watchdog timer mode is selected and the RSTE bit in RSTCSR is set to 1, if TCNT
overflows without being rewritten because of a system crash or other error, this LSI is initialized
internally. This ensures that TCNT does not overflow while the system is operating normally.
Software must prevent TCNT overflows by rewriting the TCNT value (normally H'00 is written)
before overflow occurs.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow (TCNT has overflowed), the RES pin reset has priority and the WOVF bit in
RSTCSR is cleared to 0.
The internal reset signal is output for 519 cycles of Pφ.
When RSTE = 1, a signal to initialize this LSI internally is generated. Since this signal initializes
the system click control register (SCKCR), the multiplication ratio of P φ clock is also initialized.
When RSTE = 0, the signal is not generated, meaning that the SCKCR value and multiplication
ratio of P φ clock remain unchanged.
Internal reset signal *
Notes: * If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated.
Rev. 3.00 Mar. 14, 2006 Page 372 of 804
REJ09B0104-0300
TCNT value
H'FF
H'00
H'00 written
WT/IT = 1
TME = 1 to TCNT

Figure 11.2 Operation in Watchdog Timer Mode

Overflow
WOVF = 1 WT/IT = 1
TME = 1
519 cycles
Time
H'00 written
to TCNT