Operation In Watchdog Timer Mode - Renesas H8S/2319 series Hardware Manual

11.3 Operation
11.3.1

Operation in Watchdog Timer Mode

To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent
TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs.
This ensures that TCNT does not overflow while the system is operating normally. If TCNT
overflows without being rewritten because of a system crash or other error, the WDTOVF signal *
is output. This is shown in figure 11-4. This WDTOVF signal * can be used to reset the system.
The WDTOVF signal * is output for 132 states when RSTE = 1, and for 130 states when RSTE =
0.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the chip
internally is generated at the same time as the WDTOVF signal * . The internal reset signal is
output for 518 states.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
Note: * The WDTOVF function is not available in the F-ZTAT versions.
Rev. 5.00, 12/03, page 415 of 1088