Timing Chart - Renesas HD49335HNP Specification Sheet

HD49335NP/HNP

Timing Chart

Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
0
When CDS_in input mode is used
N
CDS_in
SP1
SP2
ADCLK
D0 to D9 N 10
When ADC_in input mode is used
N
ADC_in
ADCLK
D0 to D9 N 9
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
• The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes.
• Pipe-line delay is ten clock cycles when CDSIN is used and nine when ADCIN is used.
• In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.
Rev.1.0, Feb.12.2004, page 10 of 29
1 2
N+1 N+2
N 9 N 8
N+1
N+2
N 8
~ 9
N+9
N 1
N+10
N+9
N+8
N 1 N
10 11
N+10 N+11
N
N+11
N+1