Register Descriptions; Bus Control Register 2 (Bcr2) - Renesas H8SX/1500 Series Hardware Manual

Section 6 Bus Controller (BSC)
6.2

Register Descriptions

The bus controller has the following registers.

• Bus control register 2 (BCR2)

6.2.1 Bus Control Register 2 (BCR2)
BCR2 is used for bus arbitration control of the CPU and DMAC, and enabling/disabling of the
write data buffer function to the peripheral device.
Bit 7
Bit Name —
Initial Value 0
R/W R
Bit Bit Name

7, 6

5
4 IBCCS

3, 2

1
0 PWDBE
Rev. 3.00 Mar. 14, 2006 Page 126 of 804
REJ09B0104-0300
6 5
— —
0 0
R R/W
Initial
Value R/W Description
All 0 R Reserved
These are read-only bits and cannot be modified.
0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
0 R/W Internal Bus Cycle Control Select
Selects the internal bus arbiter function.
0: Releases the bus mastership according to the priority
1: Executes the bus cycles alternatively when a CPU
All 0 R Reserved
These are read-only bits and cannot be modified.
1 R/W Reserved
This bit is always read as 1. The write value should
always be 1.
0 R/W Peripheral Module Write Data Buffer Enable
Specifies whether or not to use the write data buffer
function for the peripheral module write cycles.
0: Write data buffer function not used
1: Write data buffer function used
4 3
IBCCS —
0 0
R/W R
bus mastership request conflicts with a DMAC bus
mastership request
2 1
— — PWDBE
0 1
R R/W R/W
0
0