ST STM32L4+ Series Reference Manual page 1448

General-purpose timers (TIM15/TIM16/TIM17)
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:17 Reserved, must be kept at reset value.
Bits 15:7 Reserved, must be kept at reset value.
Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
Bit 3 OC1PE: Output Compare 1 preload enable
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
Bit 2 OC1FE: Output Compare 1 fast enable
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28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
0001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
0100: Force inactive level - OC1REF is forced low.
0101: Force active level - OC1REF is forced high.
0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive.
0111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active.
All other values: Reserved
bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output).
In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from "frozen" mode
to "PWM" mode.
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output).
The PWM mode can be used without validating the preload register only in one pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
This bit decreases the latency between a trigger event and a transition on the timer output.
It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output
pulse starting as soon as possible after the starting trigger.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input
is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC
is set to the compare level independently of the result of the comparison. Delay to
sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE
acts only if the channel is configured in PWM1 or PWM2 mode.
24 23 22
Res. Res. Res.
8 7 6
Res. Res. OC1M[2:0]
rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OC1PE OC1FE
rw rw rw rw
RM0432
17 16
OC1M
Res.
[3]
rw
1 0
CC1S[1:0]
rw rw