ST STM32L4+ Series Reference Manual page 1449

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Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection

Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).

TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17)

Address offset: 0x20

Reset value: 0x0000

Bits 15:4 Reserved, must be kept at reset value.

Bit 3 CC1NP: Capture/Compare 1 complementary output polarity

CC1 channel configured as output:

CC1 channel configured as input:

Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

Others: Reserved

0: OC1N active high

1: OC1N active low

This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer

to the description of CC1P.

in TIMx_BDTR register) and CC1S="00" (the channel is configured in output).

On channels that have a complementary output, this bit is preloaded. If the CCPC bit is

set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the

preloaded bit only when a commutation event is generated.

General-purpose timers (TIM15/TIM16/TIM17)

RM0432 Rev 6

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