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Table 24-5 Oscillation Stabilization Time Settings
STS2 STS1 STS0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
: Recommended time setting
Using an External Clock: The PLL circuit requires a time for stabilization. Insert a wait of 2 ms
min.
24.6.4
Software Standby Mode Application Example
Figure 24-3 shows an example in which a transition is made to software standby mode at the
falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.
Standby
25
20
Time
MHz
MHz
8192
0.32 0.41
states
16384
0.65 0.82
states
32768
1.3
1.6
states
65536
2.6
3.3
states
131072
5.2
6.6
states
262144
10.4
13.1 16.4
states
Reserved —
—
16 states
0.6
0.8
(Setting
prohibited)
16
12
10
8
MHz
MHz
MHz
MHz
0.51
0.65
0.8
1.0
1.0
1.3
1.6
2.0
2.0
2.7
3.3
4.1
4.1
5.5
6.6
8.2
8.2
10.9
13.1 16.4
21.8
26.2 32.8
—
—
—
—
1.0
1.3
1.6
2.0
6
4
2
MHz
MHz
MHz Unit
1.3
2.0
4.1
ms
2.7
4.1
8.2
5.5
8.2
16.4
10.9 16.4
32.8
21.8
32.8
65.5
43.6
65.6
131.2
µs
—
—
—
1.7
4.0
8.0
1003
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