Transfer Objects; Dma Channel Priorities - Renesas NU85E Preliminary User's Manual

32-bit microprocessor core
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7.3 Transfer Objects

(1) Transfer types
Table 7-1 shows the relationships between transfer types and transfer objects.
Caution Operation is not guaranteed when a transfer is performed using a combination of transfer
source and transfer destination marked by an "No" in Table 7-1.
Table 7-1. Relationships Between Transfer Type and Transfer Object
VSB
Transfer
NPB
Source
RAM
Note The transfer can be performed only when using the MEMC (NT85E500) associated with the flyby transfer.
Remark Yes: Transfer enabled
No: Transfer disabled
VSB: External memory or peripheral macro on the VSB
NPB: Peripheral macro on the NPB
RAM: RAM directly connected to the VDB
(2) Wait function
Table 7-2 shows the relationships between the wait function and transfer objects.
Table 7-2. Relationships Between Wait Function and Transfer Object
Transfer Object
VSB
NPB
RAM

7.4 DMA Channel Priorities

DMA channel prioritization is fixed as follows.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
This prioritization is only valid in the TI state. During a block transfer, the channel used for transfer is never
switched.
During a single-step transfer, if a higher priority DMA transfer request is generated during the period when the bus
is released (TI), the higher priority DMA transfer is performed.
CHAPTER 7 DMAC
Two-Cycle Transfer
VSB
NPB
Yes
Yes
Yes
Yes
Yes
Yes
Preliminary User's Manual A14874EJ3V0UM
Transfer Destination
RAM
VSB
Note
Yes
Yes
Yes
No
Yes
No
Wait Function
Set by MEMC (NT85E500, NT85E502)
Set by VSWC register
No wait
Flyby Transfer
NPB
RAM
No
No
No
No
No
No
151

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