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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
11.2. DMA Transfer Cycles
Any combination of even or odd transfer read and write adresses is possible. Table 11.2.1 shows the
number of DMA transfer cycles. Table 11.2.2 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 11.2.1 DMA Transfer Cycles
Transfer unit
8-bit transfers
(DMBIT= "1")
16-bit transfers
(DMBIT= "0")
Table 11.2.2 Coefficient j, k
Internal area
Internal ROM, RAM
No wait With wait
j
1
2
k
1
2
NOTE:
1. Depends on the set value of PM20 bit in PM2 register.
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
Access address
No. of read cycles
Even
Odd
Even
Odd
SFR
1 wait
2 wait
(1)
(1)
2
3
3
2
page 89
f o
3
2
9
6
C
2 /
6
) T
No. of write cycles
1
1
1
2
1
1
1
2
11. DMAC
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