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M16C/29 Group
2
16.5 I
C0 Status Register (S10 register)
2
The I
C0 status register (address 02E8
only if it is used for a status check.
16.5.1 Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for an ACK receive confirmation. If
the ACK is returned when the ACK clock is generated, the LRB bit is set to "0". If the ACK is not returned,
this bit is set to "1". Except in ACK mode, the last bit value of the received data is input. The bit is "0"
by executing a write instruction to the I
16.5.2 Bit 1: General call detection flag (ADR0)
When the ALS bit is "0", this bit is set to "1" when a general call
received in slave mode. By a general call of the master device, every slave device receives control data
after the general call. The ADR0 bit is set to "0" by detecting the STOP condition, START condition and
when the ES0 is "0", or reset.
Note 1. General call: The master transmits the general call address "00
16.5.3 Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of the address data when the ALS bit in the S1D0 register is "0".
In slave receive mode, this bit is set to "1" in one of the following conditions:
7 bit of the address data matches the slave address stored in the S0D0 register.
•
A general call is received.
•
The AAS flag is set to "0" in one of the following conditions:
When the ES0 bit is set to "1", excute to write an instruction to the S00 register
•
When the ES0 bit is set to "0".
•
Excute to reset by the IHR bit in the S1D0 register.
•
16.5.4 Bit 3: Arbitration lost detection flag (AL)
When devices other than the microcomputer set the S
judged to be lost and the AL bit is set to "1". At the same time, the TRX bit is set to "0". On Arbitration loss
being detected. S
lost, is completed, the MST bit is set to "0". The arbitration lost can be detected only in master transmit
mode. When the arbitration is lost during the slave address transmit, the TRX bit is set to "0" and the
receive mode is set. Consequently, it is possible to detect the match between its own slave address and
address data transmitted by another master devices. The bit becomes "0" if writing to the I
register (address 02E0
The bit also becomes "0" when the ES0 bit is set to "0" or when reset.
Do not write to S00 to clear the AL bit, delay write until master is ready for new transmit.
Note 1. Arbitration lost: The status is that communication as a master is disabled.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
) controls the I
16
2
C0 data shift register (address 02E0
is released immediately. Immediately after the byte transmist, whose arbitration is
CL
) when the ES0 bit is "1".
16
page 261 of 402
16. MULTI-MASTER I
2
C bus interface status. Use the lower-6 bit as read
16
,whose address data is all "0", is
(Note 1)
" to all slaves.
16
(Note 1)
to "L" in master transmit mode, the arbitration is
DA
2
C bus INTERFACE
).
2
C0 data shift
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