On-Chip Hcan Module Access Timing; Figure 7.3 On-Chip Hcan Module Access Cycle (Wait States Inserted) - Renesas H8S Series Hardware Manual

7.1.3

On-Chip HCAN Module Access Timing

On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait
states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access
timing is shown in figures 7.3.
φ
Internal address bus
HCAN read signal
Read
Internal data bus
HCAN write signal
Write
Internal data bus

Figure 7.3 On-Chip HCAN Module Access Cycle (Wait States Inserted)

Bus cycle
T
T T
2
1 3
Address
Rev. 6.00 Mar 15, 2006 page 99 of 570
Section 7 Bus Controller
T T T
W W 4
Read data
Write data
REJ09B0211-0600