Table 6.7 Idle Cycles In Mixed Accesses To Normal Space And Dram - Renesas H8S/2368 Series Hardware Manual

Table 6.7 shows whether an idle cycle is inserted or not in mixed access to normal space and
DRAM.
Table 6.7 Idle Cycles in Mixed Accesses to Normal Space and DRAM
Previous Access Next Access
Normal space read Normal space read
(different area)
DRAM/ space read
Normal space write
DRAM/ space write
DRAM/ space read Normal space read
DRAM/ space read
Normal space write
DRAM/ space write
ICIS2 ICIS1 ICIS0
— 0 —
— 1 —
— 0 —
— 1 —
— — 0
— — 1
— — 0
— — 1
— 0 —
— 1 —
— 0 —
— 1 —
— — 0
— — 1
— — 0
— — 1
DRMI IDLC Idle cycle
— — Disabled
— 0 1 state inserted
1 2 states inserted
— — Disabled
— 0 1 state inserted
1 2 states inserted
— — Disabled
— 0 1 state inserted
1 2 states inserted
— — Disabled
— 0 1 state inserted
1 2 states inserted
— — Disabled
0 — Disabled
1 0 1 state inserted
1 2 states inserted
— — Disabled
0 — Disabled
1 0 1 state inserted
1 2 states inserted
— — Disabled
0 — Disabled
1 0 1 state inserted
1 2 states inserted
— — Disabled
0 — Disabled
1 0 1 state inserted
1 2 states inserted
Rev. 2.00, 05/03, page 187 of 820