Interrupt Control Register 1 (Icr1) - Renesas HD6417641 Hardware Manual

Section 10 Interrupt Controller (INTC)
10.3.3

Interrupt Control Register 1 (ICR1)

ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ5 to
IRQ0 individually: rising edge, falling edge, high level, or low level. This register is initialized to
H'4000 by a power-on reset or manual reset, but is not initialized in standby mode.
Bit Bit Name

15
14 IRQE*

13, 12
11 IRQ51S
10 IRQ50S
9 IRQ41S
8 IRQ40S
7 IRQ31S
6 IRQ30S
5 IRQ21S
4 IRQ20S
3 IRQ11S
2 IRQ10S
1 IRQ01S
0 IRQ00S
Note: * The IRQE bit must be cleared to 0 in the initialization routine after a reset, and must then
not be changed.
Rev. 4.00 Sep. 14, 2005 Page 226 of 982
REJ09B0023-0400
Initial
Value R/W Description
0 R Reserved
This bit is always read as 0. The write value should
always be 0.
1 R/W Interrupt Request Enable
Enables or disables the use of pins IRQ7 to IRQ0 as
eight independent interrupt pins.
0: Use of pins IRQ7 to IRQ0 as eight independent
interrupt pins enabled*
1: Use of pins IRQ7 to IRQ0 as interrupt pins disabled
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0 R/W IRQn Sense Select
0 R/W These bits select whether interrupt request signals
corresponding to pins IRQ5 to IRQ0 are detected by a
0 R/W
rising edge, falling edge, high level, or low level.
0 R/W
Bit 2n+1 Bit 2n
0 R/W
IRQn1S IRQn0S
0 R/W
0
0 R/W
0 R/W
0
0 R/W
1
0 R/W
0 R/W
1
0 R/W
n = 0 to 5
0 : Interrupt request is detected on falling
edge of IRQn input
1 : Interrupt request is detected on rising
edge of IRQn input
0 : Interrupt request is detected on low
level of IRQn input
1 : Interrupt request is detected on high
level of IRQn input