Serirq Control Registers 0 And 1 (Sirqcr0, Sirqcr1) - Renesas H8S/2111B Hardware Manual

Bit Bit Name
2 SMIE2
1 IRQ12E1
R/W
Initial Hos
Value Slave t
0 R/W —
0 R/W —
Description
Host SMI Interrupt Enable 2
Enables or disables a host SMI interrupt request when
OBF2 is set by an ODR2 write.
0: Host SMI interrupt request by OBF2 and SMIE2 is
disabled
[Clearing conditions]
•
Writing 0 to SMIE2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host SMI interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
Host SMI interrupt is requested
[Setting condition]
•
Writing 1 after reading SMIE2 = 0
Host IRQ12 Interrupt Enable 1
Enables or disables a host IRQ12 interrupt request
when OBF1 is set by an ODR1 write.
0: Host IRQ12 interrupt request by OBF1 and IRQ12E1
is disabled
[Clearing conditions]
•
Writing 0 to IRQ12E1
•
LPC hardware reset, LPC software reset
•
Clearing OBF1 to 0
1: Host IRQ12 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
•
Writing 1 after reading IRQ12E1 = 0
Rev. 1.00, 05/04, page 389 of 544