Standby Control Register (Sbycr) - Renesas H8SX/1520 Series Hardware Manual

19.2.1

Standby Control Register (SBYCR)

SBYCR controls software standby mode.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
15 SSBY

14

13
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15 14

SSBY
0 1
R/W R/W
7 6
 
0 0
R/W R/W
Initial
Value R/W
0 R/W
1 R/W
0 R/W
13 12

STS4 STS3
0 0
R/W R/W
5 4
 
0 0
R/W R/W
Description
Software Standby
Specifies the transition mode after executing the SLEEP
instruction
0: Shifts to sleep mode after the SLEEP instruction is
executed
1: Shifts to software standby mode after the SLEEP
instruction is executed
This bit does not change when clearing the software
standby mode by using external interrupts and shifting to
normal operation. For clearing, write 0 to this bit. When
the WDT is used as the watchdog timer, the setting of this
bit is disabled. In this case, a transition is always made to
sleep mode or all-module-clock-stop mode after the
SLEEP instruction is executed.
Reserved
This bit is always read as 1. The write value should
always be 1.
Reserved
This bit is always read as 0. The write value should
always be 0.
Section 19 Power-Down Modes
11 10
STS2 STS1
1 1
R/W R/W
3 2
 
0 0
R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 673 of 804
9 8
STS0
1 1
R/W R/W
1 0
 
0 0
R/W R/W
REJ09B0104-0300