Register Descriptions; Standby Control Register (Sbycr) - Renesas H8S/2437 Hardware Manual

22.1

Register Descriptions

The registers relating to the power-down mode are shown below. For details on the system clock
control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR).
• System clock control register (SCKCR)

• Standby control register (SBYCR)

• Module stop control registers H and L (MSTPCRH, MSTPCRL)
• Extension module stop control registers H and L (EXMSTPCRH, EXMSTPCRL)
22.1.1 Standby Control Register (SBYCR)
SBYCR performs software standby mode control.
Bit Bit Name
7 SSBY
6 OPE
Rev. 1.00, 09/03, page 622 of 704
Initial Value R/W
0 R/W
1 R/W
Description
Software Standby
Specifies the transition mode after executing the
SLEEP instruction.
0: Shifts to sleep mode after the SLEEP instruction
is executed
1: Shifts to software standby mode after the
SLEEP instruction is executed
This bit does not change when clearing software
standby mode by using external interrupts and
shifting to normal operation. Write 0 to this bit
when clearing.
Output Port Enable
Specifies whether the states of the address bus
and bus control signals (CS1 to CS3, AS/AH, RD,
HWR, LWR) are retained or set to the high-
impedance state in software standby mode.
0: In software standby mode, address bus and bus
control signals are high-impedance
1: In software standby mode, address bus and bus
control signals retain the previous states