Standby Control Register (Sbycr) - Renesas H8SX/1500 Series Hardware Manual

19.2.1

Standby Control Register (SBYCR)

SBYCR controls software standby mode.
Bit 15
Bit Name SSBY
Initial Value 0
R/W R/W
Bit 7

Bit Name
Initial Value 0
R/W R/W
Bit Bit Name
15 SSBY

14

13
14 13
 
1 0
R/W R/W
6 5
 
0 0
R/W R/W
Initial
Value R/W Description
0 R/W Software Standby
Specifies the transition mode after executing the SLEEP
instruction
0: Shifts to sleep mode after the SLEEP instruction is
1: Shifts to software standby mode after the SLEEP
This bit does not change when clearing the software
standby mode by using external interrupts and shifting to
normal operation. For clearing, write 0 to this bit. When
the WDT is used as the watchdog timer, the setting of this
bit is disabled. In this case, a transition is always made to
sleep mode or all-module-clock-stop mode after the
SLEEP instruction is executed.
1 R/W Reserved
This bit is always read as 1. The write value should
always be 1.
0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
12 11
STS4 STS3
0 1
R/W R/W
4 3
 
0 0
R/W R/W
executed
instruction is executed
Rev. 3.00 Mar. 14, 2006 Page 673 of 804
Section 19 Power-Down Modes
10 9
STS2 STS1
1 1
R/W R/W
2 1
 
0 0
R/W R/W
REJ09B0104-0300
8
STS0
1
R/W
0

0
R/W