Clock Output Configuration Register - Samsung S5PC110 Manual

S5PC110_UM

3.7.6 CLOCK OUTPUT CONFIGURATION REGISTER

Internal clocks can be monitored through XCLKOUT PAD. CLK_OUT register selects an internal clock among PLL
outputs, USBPHY output, HDMIPHY output, RTC, TICK, system bus clocks, ARMCLK, HPM clock and external
OSCs. It also divides the selected clock. This is just for debugging. Do not supply this to other components as
clock.
3.7.6.1 Clock Output Configuration Register (CLK_OUT, R/W, Address = 0xE010_0500)
CLK_OUT Bit
Reserved [31:24]
DIVVAL [23:20]
Reserved [19:17]
CLKSEL [16:12]
DCLKCMP [11:8]
DCLKDIV [7:4]
Reserved
Divide ratio (Divide ratio = DIVVAL + 1)
Reserved
00000 = FOUTAPLL/4
00001 = FOUTMPLL/2
00010 = FOUTEPLL
00011 = FOUTVPLL
00100 = SCLK_USBPHY0
00101 = SCLK_USBPHY1
00110 = SCLK_HDMIPHY
00111 = RTC
01000 = RTC_TICK_SRC
01001 = HCLK_MSYS
01010 = PCLK_MSYS
01011 = HCLK_DSYS
01100 = PCLK_DSYS
01101 = HCLK_PSYS
01110 = PCLK_PSYS
01111 = ARMCLK/4
10000 = SCLK_HPM
10001 = XXTI
10010 = XUSBXTI
10011 = DCLK
DCLKCMP, DCLKDIV, DCLKSEL, and DCLKEN fields define
DCLK.
This field changes the clock duty of DCLK. Thus, it must be smaller
than DCLKDIV. It is valid only when CLKSEL is DOUT.
If the DCLKDIV is n, low level duration is (n+1).
High level duration is ((DCLKDIV + 1) - (n+1))
DCLK divide value
DCLK frequency = source clock / (DCLKDIV + 1)
Description
3 CLOCK CONTROLLER
Initial State
0x000
0x0
0x000
0x0
0x0
0x0
3-51