Onenand Interface Configuration - Samsung S5PC110 Manual

S5PC110_UM
To reduce the power consumption for OneNAND interface and drive the clock output to OneNAND device, the
gated clock output is supported. If this feature is enabled, the OneNAND device clock is toggled only if the
OneNAND device is accessed to perform read or write operation. For more information, refer to the OneNAND
Interface Control (ONENAND_IF_CTRL) register.
The warm reset operation is supported. For more information, refer to the OneNAND Interface Command
(ONENAND_IF_CMD) register.

3.6.2 ONENAND INTERFACE CONFIGURATION

There are two configuration registers for the OneNAND Interface, namely:
1. OneNAND Interface Control (OneNAND_IF_CTRL) register
2. OneNAND Interface Asynchronous Timing Control (OneNAND_IF_ASYNC_TIMING_CTRL) register.
The OneNAND Interface Control Register (ONENAND_IF_CTRL) register holds configuration bits for following:
−
MUX : Mux/ Demux select (mux-type or demux-type)
−
GCE: Gated-clock enable (enable or disable)
−
RPE: Read prefetch enable (enable or disable)
−
RM : Read mode (synchronous vs. asynchronous)
−
BRWL: Burst read write latency (3 clock, ... , 7 clock)
−
BL: Burst length (4-/8-/16-/32-/1024-burst or continuous)
−
HF: High frequency (enable or disable)
−
WM : Write mode (synchronous vs. asynchronous)
The OneNAND controller requires a correct operation sequence to change the OneNAND Interface Control
(ONENAND_IF_CTRL) register value. To update this register the system software must follow the specific
sequence illustrated in
confirm that there is no bus transaction in progress on the OneNAND interface before write new configuration to
the OneNAND Interface Control (ONENAND_IF_CTRL) register. Also note that the System Configuration 1
registers of all the OneNAND devices must be set by the same configuration value though the OneNAND interface
supports multiple (up to eight) OneNAND devices.
The OneNAND Interface Asynchronous Timing Control (ONENAND_IF_ASYNC_TIMING_CTRL) register holds
configuration bits for following:
−
WHL: nWE signal high length (1 clock, ... , 15 clock)
−
WLL: nWE signal low length (1 clock, ... , 15 clock)
−
OHL: nOE signal high length (1 clock, ... , 15 clock)
−
OLL: nOE signal low length (2 clock, ... , 16 clock)
The OneNAND controller requires a correct operation sequence to change the OneNAND Interface Asynchronous
Timing Control (ONENAND_IF_ASYNC_TIMING_CTRL) register value. To update this register the system
software must follow the specific sequence illustrated in
Busy(ORWB) bit must be checked to confirm that there is no bus transaction in progress on the OneNAND
interface before write new configuration to the OneNAND Interface Asynchronous Timing Control
(ONENAND_IF_ASYNC_TIMING_CTRL) register.
3-4. Note that the OneNAND Read Write Busy (ORWB) bit must be checked to
Figure
3-6. Note that the OneNAND Read Write
Figure
3 ONENAND CONTROLLER
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