Samsung S5PC110 Manual page 863

Risc microprocessor
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S5PC110_UM
3.4.2.7 SPI TX Data Register
SPI_TX_DATA, W, Address = 0xE130_0018
SPI_TX_DATA, W, Address = 0xE140_0018
SPI_TX_DATAn
TX_DATA
3.4.2.8 SPI RX Data Register
SPI_RX_DATA0, R, Address = 0xE130_001C
SPI_RX_DATA1, R, Address = 0xE140_001C
SPI_RX_DATAn
RX_DATA
3.4.2.9 Packet Count Register
PACKET_CNT_REG0, R/W, Address = 0xE130_0020
PACKET_CNT_REG1, R/W, Address = 0xE140_0020
PACKET_CNT_REGn
PACKET_CNT_EN
COUNT_VALUE
Bit
[31:0]
This field contains the data to be transmitted over the SPI
channel.
Bit
[31:0]
This field contains the data to be received over the SPI
channel.
Bit
[16]
Enable bit for packet count
0 = Disable
1 = Enable
[15:0]
Packet count value
3 SERIAL PERIPHERAL INTERFACE
Description
Description
Description
Initial State
0
Initial State
0
Initial State
0
0
3-15

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