Samsung S5PC110 Manual page 676

S5PC110_UM
Table 5-1
describes the timing parameters of PIO modes.
Table 5-1
The shows the timing cycle of the true IDE PIO mode, if ATA controller is in the ATA_TRANS state.
Figure 5-2
The figure indicates various timing parameters. Timing 't1' indicates the time between address valid and
IORD/IOWR asserted. Timing 't2' indicates the time for which IORD/ IOWR is asserted. The ATA state transfer in
PDMA class follows similar timing.
CS 0, CS 1,
DA [2:0]
DIOR -/
DIOW -
WR
DD [ 15 :0] or
DD [7:0]
RD
DD [ 15 :0] or
DD [7:0]
t 1
Figure 5-2
t 2
PIO Mode Waveform
5 COMPACT FLASH CONTROLLER
teoc
t 1
5-4