Tick Generation With Fractional Divider - Samsung S5PC110 Manual

S5PC110_UM

2.5 TICK GENERATION WITH FRACTIONAL DIVIDER

System timer uses fractional divider to generate tick with any input clock. Especially, system timer can make
approximate 1ms tick with RTC input clock (32.768 kHz).
The output clock from fractional divider can have local frequency error. If local frequency error is not important for
some applications, you can use that output clock with low-power consumption.
shows a simple example describing theory of fractional divider. As shown in
Figure 2-5
divider can generate any output clock with changing clock duty.
Although local frequency error exists (1.667Hz and 2.5Hz in this case), there is no global frequency error. If output
clock frequency is much slower than input clock frequency, the instance of local frequency error decreases.
To configure fractional divider divider mux and pre-scaler cannot be used for fractional divider. (write
TCFG[10:0] as 0)
Write TCFG[14] as 1.
1. General
Write TCFG[15] as 0.
Input frequency must be 4 times larger than target frequency.
VALUE = Frequency of TCLKB / 2 / target frequency
If VALUE is fractional number (a.b), write TICNTB as a-1, and TFCNTB as b*65536.
For example, if you want to generate 2kHz output with 9kHz input, VALUE is 9 / 2 / 2 = 2.25. It means that a is
2 and b is 0.25. Write TICNTB as 1 (= 2 -1) and TFCNTB as 16384 (= 0.25*65536) in this case.
NOTE: If TFCNTB is not integer number, fractional divider inevitably generates timing error. SEC can give timing error table
to determine whether you can use system timer or not for specific application.
If you require timing error table contact SEC.
Figure 2-5 Approximate 5Hz tick with 2Hz input clock
2 SYSTEM TIMER
2-5, the fractional
Figure
2-4