Samsung S5PC110 Manual page 445

S5PC110_UM
5.5.2.26 IEC Integration Test Control Register (IECITCR, R/W, Address = 0xE080_0F00)
IECITCR
-
DPM Counter Test
DVS Emulation
Slot Counter Test
ITEN
Bit
[31:3] Reserved. Unpredictable when read. Should be written as
zero.
[2] Enable or disable test mode for all DPM counters.
0 = DPM counter test mode disabled, also the reset value.
1 = DPM counter test mode enabled.
When this bit is set, the 64-bit DPM counters are split up into
eight separate 8-bit counters, each accumulate by the CPU or
programmed rate. This reduces the testing time required to
ensure that all bits of the counters toggle correctly.
[1] Enable or disable test mode for the bus V slotcounter.
0 = DVS emulation slot counter test mode disabled, also reset
value.
1 = DVS emulation slot counter test mode enabled.
When this bit is set, the 10-bit DVS emulation slot timing
counter is split up into two 5-bit counters, each decrement
separately. This reduces the testing time required to ensure
that all bits of the counters toggle correctly.
[0] Integration test enable. When this bit is set to 1, the IEC is put
into integration test mode. When 0, the IEC is in normal
operating mode. The reset value is 0.
5 INTELLIGENT ENERGY MANAGEMENT
Description Initial State
0
0
0
0
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