Page 1 S3C6400X USER’S MANUAL Preliminary_Revision 0.2 (Oct. 2007)
Page 2: Important Notice
Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
Page 3: Document Revision History
S3C6400 RISC MICROPROCESSOR DOCUMENT REVISION HISTORY DOCUMENT REVISION HISTORY The following table shows the revision history for this document. Version Date Revision Descriptions June 05, 2007 Initial Release. Chapter 1, 3, 4, 6, 7, 8, 9, 10, 11, 14, 15, 16, 17, 22, 26, 31, 32, 33, Oct 12 , 2007 36, 38, 41 Modified Preliminary product information describe products that are in development,...
Page 4: Product Overview
S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW PRODUCT OVERVIEW Architectural Overview The S3C6400 is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, low-power capabilities, high performance Application Processor solution for mobile phones and general applications. To provide optimized H/W performance for the 2.5G & 3G communication services, the S3C6400 adopts a 64/32-bit internal bus architecture.
Page 5 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR FEATURES This section summarizes the features of the S3C6400. Figure 1-1 is an overall block diagram of the S3C6400. Figure 1-1 S3C6400 block diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 6 RISC MICROPROCESSOR PRODUCT OVERVIEW 1.1.1 S3C6400X RISC Microprocessor Features Summary The features of S3C6400X RISC Microprocessor include: The ARM1176JZF-S based CPU subsystem with Java acceleration engine and 16KB/16KB I/D Cache and 16KB/16KB I/D TCM. 400Mhz Operating Frequency at 1.0 V , 533Mhz at 1.1V and 667Mhz at TBD V respectively.
Page 7 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR 1.1.2 Microprocessor The ARM1176JZF-S processor incorporates an integer unit that implements the ARM11 ARM architecture v6. It supports the ARM, Thumb™ instruction sets and Jazelle technology to enable direct execution of Java bytecodes, and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers. The features of ARM1176JZF-S processor include: TrustZone™...
Page 8 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW 1.1.3 Memory Subsystem The S3C6400 microprocessor provides the following Memory Subsystem features: High bandwidth Memory Matrix subsystem Two independent external memory ports (1 Static-DRAM Hybrid Memory port and 1 DRAM ports) Matrix architecture increases overall bandwidth with the simultaneous access capability 1.1.3.1 Static-DRAM Hybrid Memory port configurable to support the following memory types: Support SRAM/ROM/NOR Flash Interface x8 or x16 data bus...
Page 9 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR 1.1.3.2 DRAM port configurable to support the following memory types: SDRAM Interface x32 data bus 1.8/ 2.5V interface voltage Density support: up to 2Gb Mobile SDRAM Interface x32 data bus with 133Mbps/pin data rate 133MHz address and command bus speed 1.8/ 2.5V interface voltage Density support: up to 2Gb Mobile SDRAM feature support:...
Page 10 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW 1.1.4.2 Multi Standard Codec (MSC) Multi Standard Video Codec MPEG-4 part-II simple profile encoding/decoding H.264/AVC baseline encoding/decoding H.263 profile3 encoding/decoding VC1 decoding Multi-part cell and Multi Standard are supported Encoding tools [-16,+16] 1/2 and 1/4 pel accuracy motion estimation using the full-search algorithm Variable block sizes : 16x16, 16x8, 8x16 and 8x8 Unrestricted motion vector MPEG-4 AC/DC prediction...
Page 11 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR 1.1.7 Display Control The S3C6400 microprocessor provides the following Display Control features: 1.1.7.1 TFT LCD Interface 1/2/4/8bpp Palletized or 8/16/18/24-bpp Non-Palletized Color-TFF support 320x240, 640x480 or other display resolutions up to 1024x1024 Maximum 2K x 2K virtual screen size Support 5 Window Layer for PIP or OSD Realtime overlay plane multiplexing Programmable OSC window positioning...
Page 12 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW 1.1.8.3 IIS-Bus Stereo DAC Interface 1-ch IIS-bus for the audio-codec interface Optional DMA-based operation Serial, 8/16-bit per channel data transfers Supports IIS, MSB-justified and LSB-justified data format Can operate in Master or Slave mode Various bit clock frequency and codec clock frequency support 16,24,32,48 fs of bit clock frequency and 256,384,512,768 fs of codec clock frequency 1.1.9 USB Support The S3C6400 microprocessor provides the following USB Support features:...
Page 13 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR 1.1.11.2 IIC-Bus Interface 1-ch Multi-Master IIC-Bus Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in the standard mode up to 400 Kbit/s in the fast mode 1.1.11.3 SPI Interface 2ch Serial Peripheral Interface 64byte buffters for receive/transmit DMA-based or interrupt-based operation...
Page 14 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW 1.1.14.2 A/D Converter and Touch Screen Interface 8-ch multiplexed ADC Max. 500K samples/sec and 10-bit resolution 1.1.15 Storage Devices The S3C6400 microprocessor provides the following Storage Devices features: 1.1.15.1 MMC/SD Host Multimedia Card Protocol version 4.0 compatible SD Memory Card Protocol version 1.0 compatible 128 words FIFO for Tx/Rx DMA based or Interrupt based operation...
Page 15 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR 1.1.16.3 TrustZone Interrupt Controller Provides a software interface to the secure interrupt system in a TrustZone design nFIQ generation, under secure control, from any system interrupt source Masking of chosen nFIQ interrupt from non-secure interrupt controller 1.1.16.4 TrustZone Protection Controller Provides a software interface to the protection bits in a secure system in a TrustZone design Protection bits to enable programming of up to 24 areas of memory as secure or non-secure...
Page 16 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW Electrical Characteristics Operating Conditions Supply Voltage for Logic Core: VDD_INT 1.0V, VDD_ARM depends on Operation Frequency External Memory Interface: 1.8/ 2.5V External I/O Interface: 1.8/2.5/3.3V Operational Frequency 400Mhz@ VDD_ARM 1.0V 533Mhz@ VDD_ARM 1.1V Max. 667MHz@ TBD V Package 424-Pin FBGA For Small Form Factor application, POP(Package on Package) option MCP is allowed.
Page 17 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR Pin Assignments #A1 INDEX MARK Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-14...
Page 18 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 424-Pin FBGA Pin Assignments – Pin Number Order Pin Name Pin Name Pin Name Number Number Number XPCMEXTCLK1/GP NC_C XPCMSOUT1/GPE4 XPCMSOUT0/GPD4 XPCMSIN0/GPD3 XPCMFSYNC1/GPE2 XPCMEXTCLK0/GP VDDPCM XPCMDCLK1/GPE0 XM1DQM0 XM1DATA0 XM1DATA4 XM1DATA1 XM1DATA3 XM1DATA2 VDDI VDDM1 XM1DATA5 VDDARM...
Page 19 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR Table 1-1. 424-Pin FBGA Pin Assignments – Pin Number Order Pin Name Pin Name Pin Name Number Number Number VDDARM XM0ADDR8/GPO8 XM1DATA27 XPCMFSYNC0/GPD2 XM0ADDR6/GPO6 XM1DATA30 XPCMDCLK0/GPD0 VDDARM VDDI VDDARM VDDM0 XM0ADDR13/GPO13 XM1DQS0 XCIPCLK/GPF2 XM0ADDR15/GPO15 XM1DATA15 XM1DATA24 XM0ADDR12/GPO12 XM1DATA11...
Page 20 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 424-Pin FBGA Pin Assignments – Pin Number Order Pin Name Pin Name Pin Name Number Number Number VDDARM XM1ADDR12 XM1WEN XM0ADDR14/GPO14 XM1ADDR5 VDDI VSSMEM XM0DQM0 XM1ADDR10 XM0ADDR9/GPO9 XM0DATA13 XM1CKE1 XMMCCLK1/GPH0 XM0SMCLK/GPp1 XHIDATA17/GPL14 VSSIP XM0OEN XM0DATA1 VSSPERI...
Page 21 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR Table 1-1. 424-Pin FBGA Pin Assignments – Pin Number Order Pin Name Pin Name Pin Name Number Number Number VSSMEM XM0DQS0/GPQ5 XHIADR8/GPL8 VSSIP XEFFVDD VDDM0 XHIDATA11/GPK11 VSSMPLL XM0DQS1/GPQ6 XHIDATA9/GPK9 XHIADR7/GPL7 XM0CKE/GPQ4 XUHDN XHIADR9/GPL9 XM0WEATA/GPP12 XHIDATA10/GPK10 XHIDATA1/GPK1 VSSEPLL VDDHI...
Page 22 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 424-Pin FBGA Pin Assignments – Pin Number Order Pin Name Pin Name Pin Name Number Number Number XM0INPACKATA/GPP AB25 XVVD20/GPJ4 VSSAPLL VSSMEM XM0REGATA/GPP11 XADCAIN0 XOM1 AA23 XHICSN/GPM0 XADCAIN1 VDDALIVE AA24 XVDEN/GPJ10 XADCAIN7 XEXTCLK AA25 XVHSYNC/GPJ8 VDDADC...
Page 23 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR Table 1-1. 424-Pin FBGA Pin Assignments – Pin Number Order Pin Name Pin Name Pin Name Number Number Number AC25 XVVD19/GPJ3 AD25 NC_I NC_G NC_H XADCAIN2 XADCAIN4 XADCAIN3 XADCAIN6 XADCAIN5 XDACOUT1 VSSADC XDACIREF VDDDAC XDACVREF XUSBXTI VSSOTG XUSBXTO...
Page 24: Pin Description
S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW Pin Description 1.1.18.1 External Memory Interface • Shared Memory Port (SROMC / OneNAND / NAND / ATA / DRAM0) Function Signal Xm0DQM[1:0] 2’b11 2’b11 2’b11 Xm0CSn[1:0] Xm0CSn[3:2] GPO[1:0] EINT7[1:0] Xm0CSn[5:4] GPO[3:2] EINT7[3:2] Xm0CSn[7:6] GPO[5:4] EINT7[5:4] Xm0ADDR[5:0] ADDR 6’h0...
Page 25 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR Function Signal Xm0INTata GPP[8] EINT8[8] Xm0RESETata RESET GPP[9] EINT8[9] Xm0INPACKata INPACK GPP[10] EINT8[10] Xm0REGata GPP[11] EINT8[11] Xm0WEata GPP[12] EINT8[12] Xm0OEata GPP[13] EINT8[13] Xm0CData GPP[14] EINT8[14] Signal Description ADDR[15:0] Memory port 0 common address bus DATA[15:0] Memory port 0 common data bus nCS[7:6] Memory port 0 DRAM Chip Select support up to 2 memory bank...
Page 26 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW Memory port 0 CF CARD Reset RESET INPACK Memory port 0 CF Input acknowledge in I/O mode Memory port 0 CF Interrupt request from CF card Memory port 0 CF Write enable strobe Memory port 0 CF Output enable strobe Memory port 0 CF Card detection DQM[1:0] Memory port 0 DRAM Data Mask...
Page 27 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR Signal Description Xm1CKE[1:0] Memory port 1 DRAM Clock Enable Xm1SCLK Memory port 1 DRAM Clock Xm1SCLKn Memory port 1 DRAM Inverted Clock of Xm1SCLK Xm1CSn[1:0] Memory port 1 DRAM Chip Select support up to 2 memory bank. Xm1ADDR[15:0] Memory port 1 DRAM Address bus Xm1RASn...
Page 28 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW Signal Description XuRXD[0] UART 0 receives data input UART 0 transmits data output XuTXD[0] XuCTSn[0] UART 0 clear to send input signal UART 0 request to send output signal XuRTSn[0] XuRXD[1] UART 1 receives data input XuTXD[1] UART 1 transmits data output XuCTSn[1]...
Page 29 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR EINT2[2 XspiMOSI[0] IO IO GPC[2] XspiMOSI[0] ADDR_CF[2] EINT2[3 XspiCS[0] IO IO GPC[3] XspiCS[0] EINT2[4 XspiMISO[1] IO IO IO O GPC[4] XspiMISO[1] XmmcCMD2 EINT2[5 XspiCLK[1] IO IO O O GPC[5] XspiCLK[1] XmmcCLK2 EINT2[6 XspiMOSI[1] IO IO GPC[6] XspiMOSI[1] EINT2[7...
Page 30 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW XpcmFSYNC[1] O IO O XpcmFSYNC[1] Xi2sLRCK[1] X97SYNC GPE[2] XpcmSIN[1] XpcmSIN[1] Xi2sDI[1] X97SDI GPE[3] XpcmSOUT[1] O O O XpcmSOUT[1] Xi2sDO[1] X97SDO GPE[4] Signal Description XpcmDCLK[0] PCM Serial Shift Clock XpcmEXTCLK[0] optional reference clock (divided internally to generate PCM timing and XpcmDCLK) PCM Sync indicating start of word XpcmFSYNC[0] PCM Serial Data Input...
Page 31 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR XusbDM USB Data pin DATA(-) XusbXTI Crystal Oscillator XI signal XusbXTO Crystal Oscillator XO signal XusbREXT External 3.4k-ohm (+/- 1%) resistor connection XusbVBUS USB Mini-Receptacle Vbus XusbID USB Mini-Receptacle Identifier XusbDRVVBUS Drive Vbus for Off-Chip Charge Pump 1.1.18.3 Parallel Communication •...
Page 32 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW XhiWEn XhiWEn XEINT[26] DATA_CF[13] IOWR_CF GPM[3] XhiOEn XhiOEn XEINT[27] DATA_CF[14] IORDY_CF GPM[4] XhiINTR XhiINTR DATA_CF[15] GPM[5] Xhi A DDR[2:0] Xhi A DDR[2:0] XkpCOL[2:0] ADDR_CF[2:0] GPL[2:0] Xhi A DDR[7:3] Xhi A DDR[7:3] XkpCOL[7:3] GPL[7:3] Xhi A DDR[8] XhiADDR[8] XEINT[16] CE_CF[0]...
Page 33 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR XhrxFLAG (Modem to Application Processor) Bit transmission in both directions occurs over a two-wire (DATA+FLAG) serial interface. The bits are transmitted sequentially, starting with the most significant bit of the physical layer frame. The DATA line always reflects the value being XhrxDATA transmitted and the FLAG only toggles when the bit value transmitted remains constant.
Page 34 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW 1.1.18.5 Image/Video Processing • Camera Interface Function Signal XciCLK GPF[0] EINT4[0] XciCLK XciHREF XciHREF GPF[1] EINT4[1] XciPCLK XciPCLK GPF[2] EINT4[2] XciVSYNC XciVSYNC GPF[3] EINT4[3] XciRSTn XciRSTn GPF[4] EINT4[4] XciYDATA[0] XciYDATA[0] GPF[5] EINT4[5] XciYDATA[1] XciYDATA[1] GPF[6] EINT4[6] XciYDATA[2] XciYDATA[2]...
Page 35 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR XvVD[22] IO XvVD[22]: LCD pixel data output XvSYS_VSYNC_LDI : i80 for RGB interface VSYNC interface control XvVD[23] IO XvVD[23]: LCD pixel data output XvSYS_OEn : i80 Output for RGB interface Enable control XvVCLK IO XvVCLK: Pixel clock signal for XvSYS_Wen: i80 Write RGB interface Enable control...
Page 36 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW 1.1.18.7 Storage Devices • MMC 2 channel Signal Function GPG[0] EINT5[0] XmmcCLK0 XmmcCLK0 ADDR_CF[0] GPG[1] EINT5[1] XmmcCMD0 XmmcCMD0 ADDR_CF[1] GPG[2] EINT5[2] XmmcDAT0[0] XmmcDAT0[0] ADDR_CF[2] GPG[3] EINT5[3] XmmcDAT0[1] XmmcDAT0[1] GPG[4] EINT5[4] XmmcDAT0[2] XmmcDAT0[2] GPG[5] EINT5[5] XmmcDAT0[3] XmmcDAT0[3] GPG[6] EINT5[6]...
Page 37 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR 1.1.18.8 System Management • Reset Signal Description XnRESET XnRESET suspends any operation in progress and places S3C6400 into a known reset state. For a reset, XnRESET must be held to L level for at least 4 FCLK after the processor power has been stabilized.
Page 38 S3C6400 RISC MICROPROCESSOR PRODUCT OVERVIEW • MISC Signal Description XOM[4:0] Operation mode selection. Refer System controller XPWRRGTON Power Regulator enable XSELNAND Select Flash Memory. 0 : OneNAND, 1 : NAND. XnBATF Battery fault indication 1.3.1.9 Power -supply Groups • Signal Description Voltage VDDALIVE...
Page 39 PRODUCT OVERVIEW S3C6400 RISC MICROPROCESSOR VSSOTGI Internal Ground for USB OTG PHY VSSPERI IO ground for USB HOST, SDMMC, Host I/F, LCD, PCM, External I/F and System Controller VSSAPLL Ground for APLL core VSSMPLL Ground for MPLL core VSSEPLL Ground for EPLL core VSSADC Ground for ADC core VSSDAC...
Page 40 S3C6400X RISC MICROPROCESSOR MEMORY MAP MEMORY MAP 2.1 MEMORY SYSTEM BLOCK DIAGRAM Figure 2-1 Address Map Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 41 MEMORY MAP S3C6400X RISC MICROPROCESSOR S3C6400X supports 32-bit physical address field and that address field can be seperated into two parts, one part is for memory, the other part is for pheriperal. Main memory is accessed via SPINE bus, and its address range is from 0x0000_0000 to 0x6FFF_FFFF. This main memory part is seperated into four areas, boot image area, internal memory area, static memory area, and dynamic memory area.
Page 42 S3C6400X RISC MICROPROCESSOR MEMORY MAP 2.2 DEVICE SPECIFIC ADDRESS SPACE Address Size(MB) Description Note Remap 0 : SRAM0 or Boot Loader Mirrored 0x0000_0000 0x07FF_FFFF 128MB Remap 1 : Internal ROM Region 0x0800_0000 0x0BFF_FFFF 64MB Internal ROM 0x0C00_0000 0x0FFF_FFFF 64MB Stepping Stone (Boot Loader)
Page 43 MEMORY MAP S3C6400X RISC MICROPROCESSOR AHB BUS MEMORY MAP Address Description Note 0x7000_0000 0x700F_FFFF SROM SFR 0x7010_0000 0x701F_FFFF OneNAND SFR 0x7020_0000 0x702F_FFFF NFCON SFR 0x7030_0000 0x703F_FFFF CFCON SFR 0x7040_0000 0x70FF_FFFF Reserved 0x7100_0000 0x710F_FFFF TZIC0 0x7110_0000 0x711F_FFFF TZIC1 0x7120_0000 0x712F_FFFF INTC0...
Page 44 S3C6400X RISC MICROPROCESSOR MEMORY MAP APB BUS MEMORY MAP Address Description Note 0x7640_0000 0x76FF_FFFF Reserved 0x7700_0000 0x770F_FFFF Post Processor 0x7710_0000 0x771F_FFFF LCD Controller 0x7720_0000 0x772F_FFFF Rotator 0x7730_0000 0x77FF_FFFF Reserved 0x7800_0000 0x783F_FFFF Camera I/F 0x7840_0000 0x787F_FFFF Reserved 0x7880_0000 0x78BF_FFFF JPEG 0x78C0_0000...
Page 45 MEMORY MAP S3C6400X RISC MICROPROCESSOR APB BUS MEMORY MAP Address Description Note 0x7DD0_0000 0x7DFF_FFFF Reserved 0x7E00_0000 0x7E00_0FFF DMC0 SFR 0x7E00_1000 0x7E00_1FFF DMC1 SFR 0x7E00_2000 0x7E00_2FFF MFC SFR 0x7E00_3000 0x7E00_3FFF Reserved 0x7E00_4000 0x7E00_4FFF Watch-Dog Timer 0x7E00_5000 0x7E00_5FFF 0x7E00_6000 0x7E00_6FFF HSI TX...
Page 46: System Controller
S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER SYSTEM CONTROLLER OVERVIEW The System Controller consists of two parts; System Clock Control and System Power-management Control. The System Clock Control logic in S3C6400 can generate the required system clock signals, ARMCLK for CPU, HCLK for AXI/AHB-bus peripherals, and PCLK for the APB bus peripherals.
Page 47 S3C6400X RISC MICROPROCESSOR Control bus priority FUNCTIONAL DESCRIPTION This section describes the functionality of S3C6400X system controller. It covers the clock architecture, reset scheme, and power management modes. HARDWARE ARCHITECTURE Figure 3-1 shows S3C6400X block diagram. S3C6400X consists of ARM1176 processor, several media co- processors and various peripheral IP’s.
Page 48 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER CLOCK ARCHITECTURE Figure 3-2 shows the block diagram of the clock generation module. The clock source selects between an external crystal (XXTIpll) and external clock (XEXTCLK). The clock generator consists of three PLL’s (Phase Locked Loop) which generate high frequency clock signals up to 1.4GHz.
Page 49 Internal clocks will be generated using external clock source as shown in Table 3-1. The OM[4:0] pins determines the operating mode of S3C6400X when the external reset signal is asserted. As shown in the Table 3-1, the OM[0] selects the external clock source, i.e., if the OM[0] is 0, the XXTIpll (external crystal) is selected. Otherwise, XEXTCLK is selected.
Page 50 Clock selection between PLL’s and input reference clock Figure 3-4 shows the clock generation logic. S3C6400X has three PLL’s which are APLL for ARM operating clock, MPLL for main operating clock, and EPLL for special purpose. The operating clocks are divided into three groups.
Page 51 S3C6400X consists of AXI bus, AHB bus, and APB bus to optimize the performance requirements. Internal IPs is connected to appropriate bus systems to meet their I/O bandwidth and operating performance. When they are attached to AXI bus or AHB bus, the operating speed can be up to 133MHz.
Page 52 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER integer value. For example, if DIV has 1 of CLK_DIV0[8], then DIV must be 1, 3, ... of CLK_DIV0[15:12]. HCLK PCLK Otherwise, the IP’s on APB bus system cannot transfer data correctly. JPEG and security sub-system on AHB bus system cannot be running at 133MHz.AHB clocks are independently...
Page 53 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR OneNAND clock generation Figure 3-7 shows clock generators for OneNAND interface controller. OneNAND interface controller requires additional synchronized clock which must be half of the other clock frequency. As shown in the Figure 3-7, the clock is generated from HCLK.
Page 54 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER Camera I/F clock generation Figure 3-9 shows the clock generator for the camera interface. All data for camera interface is transferred/received based on this clock. The maximum operating clock is up to 133MHz. Figure 3-9. Camera I/F clock generation Clock generation for display (POST, LCD, and scaler) Figure 3-10 shows the clock generator for display blocks.
Page 55 Clock generation for audio (IIS and PCM) Figure 3-11 generates special clocks for audio interface logics, which include IIS and PCM. S3C6400X has two IIS channels and two PCM channels, supports only two channels at any given time. Usually, EPLL generates one special clock for an audio interface.
Page 56 The clocks are controlled by SCLK_GATE. Clock output S3C6400X has clock output port, which generate internal clock. This clock is used for regular interrupt or debugging purpose. For more information, please refer to CLK_OUT register section. LOW POWER MODE OPERATION S3C6400X supports low power application through low power mode operation as shown in Table 3-3.
Page 57 ARM1176 must be set and retained during STOP mode. In this case, the logic power of top block should be set and the memory power of top block can be configured. Otherwise, S3C6400X may not return to the previous state.
Page 58 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER STOP mode In STOP mode, sub-power domains, which are highlighted in black boxes, are OFF with internal power-gating circuitry as shown in Figure 3-15. Other blocks which are highlighted in white boxes and ARM1176, are retaining the previous state (clock-gating state).
Page 59 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR 5. SYSCON changes clock source from external oscillator to PLL output if PLL is used. 6. SYSCON releases self-refresh mode requests to memory controllers. 7. The memory controllers send acknowledges when they are ready. 8. SYSCON releases AXI/AHB bus down request.
Page 60 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER DOMAIN DOMAIN DOMAIN DOMAIN MEMSYS AXI (64b) DOMAIN DOMAIN DOMAIN DOMAIN ARM11 AXI (32b) APB (32b) PERIPHERAL Figure 3-17. Power domains at SLEEP mode (only ALIVE and RTC keep internal state) The following are the SLEEP mode entering sequence: 1.
Page 61 Warm reset RESET S3C6400X has five types of reset signals and SYSCON can place the system into one of five resets. Hardware reset: It is generated by asserting XnRESET. It is an uncompromised, ungated, total and complete reset that is used when you do not require information in system any more. It fully initializes all system.
Page 62 XnRSET must be held long enough to allow internal stabilization and propagation of the reset state to enter proper reset state. Power regulator for S3C6400X must be stable prior to the deassertion of XnRESET. Otherwise, it may damage S3C6400X and the operation is unpredictable.
Page 63 Since the arbitration scheme and priority heavily affect on it, most bus system can configure the scheme and priority. S3C6400X also supports two bus arbitration schemes and several priority configurations. AHB_CONx registers control AHB bus arbitration scheme and priority.
Page 64 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER REGISTER DESCRIPTION System controller controls PLL, clock generator, the power management part, and other system dependent part. This section describe how to control these part using SFR(Special Functional Register) within the system controller. MEMORY MAP The followings show 34 registers within system controller.
Page 65 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR MEM_CFG_STAT 0x7E00_F12C Memory subsystem setup status 0x0000_0000 0x7E00_F200~ RESERVED RESERVED 0x7E00_F800 PWR_CFG 0x7E00_F804 Configure power manager 0x0000_0001 EINT_MASK 0x7E00_F808 Configure EINT(external interrupt) mask 0x0000_0000 RESERVED 0x7E00_F80C RESERVED NORMAL_CFG 0x7E00_F810 Configure power manager at NORMAL mode...
Page 66 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER INDIVIDUAL REGISTER DESCRIPTIONS PLL Control Registers S3C6400 has three internal PLL’s, which are APLL, MPLL, and EPLL. They are controlled by the following seven special registers. REGISTER ADDRSS DESCRIPTION RESET VALUE APLL_LOCK 0x7E00_F000 Control PLL locking period for APLL...
Page 67 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR NOTE1: The output frequency is calculated by using the following equation: SDIV = MDIV X F / (PDIV X 2 where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions : MDIV: 64 ≤ MDIV ≤ 1023 PDIV: 1 ≤...
Page 68 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER NOTE1: The output frequency is calculated by using the following equation: SDIV = (MDIV + KDIV / 2 ) X F / (PDIV X 2 where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions : MDIV: 13 ≤...
Page 69 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR Clock source control register S3C6400 has many clock sources, which include three PLL outputs, the external oscillator, the external clock, and other clock sources from GPIO configuration. CLK_SRC register controls the source clock of each clock divider.
Page 70 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER MFCCLK_SEL Control MUXMFC, which is the source clock of MFC RESERVED RESERVED EPLL_SEL Control MUX (0:FIN , 1:FOUT EPLL EPLL EPLL MPLL_SEL Control MUX (0:FIN , 1:FOUT MPLL MPLL MPLL APLL_SEL Control MUX (0:FIN , 1:FOUT...
Page 71 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 3-26 Specifications and information herein are subject to change without notice.
Page 72 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER Clock divider control register S3C6400 has several clock dividers to support various operating clock frequency. The clock divider ratio can be controlled by CLK_DIV0, CLK_DIV1, and CLK_DIV2. REGISTER ADDRESS DESCRIPTION RESET VALUE CLK_DIV0 0x7E00_F020 Set clock divider ratio...
Page 73 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR clock divider ratio ARM_RATIO [2:0] ARMCLK = DOUT / (ARM_RATIO + 1) APLL CLK_DIV1 controls MMC, LCD, TV scaler, and UHOST clocks. CLK_DIV1 DESCRIPTION RESET VALUE RESERVED [31:24] RESERVED USB host clock divider ratio UHOST_RATIO...
Page 74 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER Clock output configuration register Internal clocks can be monitored through GPIO port, which is GPIO port-F. CLK_OUT register selects an internal clock among PLL output, HCLK, 48MHz, 27MHz, RTC, and TICK. It also divides the selected clock.
Page 75 HCLK_GATE controls HCLK of all IPs. If a field has ‘1’, then HCLK is supplied. Otherwise, HCLK is masked. When S3C6400x goes to a power down mode, system controller checks the status of some block, IROM, MEM0, MEM1, and MFC block. Therefore, bit 25, 22, 21, 0 should be ‘1’ to acknowledge a power down request.
Page 76 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER HCLK_POST0 Gating HCLK for POST0 (0: mask, 1: pass) HCLK_ROT Gating HCLK for rotator (0: mask, 1: pass) HCLK_LCD Gating HCLK for LCD controller (0: mask, 1: pass) HCLK_TZIC Gating HCLK for trust interrupt controller (0: mask, 1: pass)
Page 77 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR SCLK_GATE DESCRIPTION RESET VALUE RESERVED [31] RESERVED SCLK_UHOST [30] Gating special clock for USB-HOST (0: mask, 1: pass) SCLK_MMC2_48 [29] Gating special clock for MMC2 (0: mask, 1: pass) SCLK_MMC1_48 [28] Gating special clock for MMC1 (0: mask, 1: pass)
Page 78 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER AHB bus control register Most multimedia IPs are connected through AHB 2.0 bus system. The bus priority can be controlled using the following three registers. REGISTER ADDRESS DESCRIPTION RESET VALUE AHB_CON0 0x7E00_F100 Configure AHB I/P/X/F bus...
Page 79 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR AHB_CON0 controls AHB-F, AHB-X, AHB-P, AHB-I bus systems. AHB_CON0 DESCRIPTION RESET VALUE DISABLE_HLOCK_I [31] Control HLOCK for I-block (0: disable, 1:enable) RESERVED [30] RESERVED PRIOR_TYPE_I [29:28] Arbitration type for AHB-I RESERVED [27] RESERVED FIX_PRIOR_I [26:24] Fixed priority order for AHB-I...
Page 80 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER AHB_CON1 controls AHB-T0, AHB-T1, AHB-M0, AHB-M1 bus systems. AHB_CON1 DESCRIPTION RESET VALUE DISABLE_HLOCK_M [31] Control HLOCK for M-block (0: disable, 1:enable) RESERVED [30] RESERVED PRIOR_TYPE_M1 [29:28] Arbitration type for AHB-M1 RESERVED [27] RESERVED FIX_PRIOR_M1 [26:24] Fixed priority order for AHB-M1...
Page 81 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR AHB_CON2 controls AHB-S0, AHB-S1, AHB-R bus systems. AHB_CON2 DESCRIPTION RESET VALUE RESERVED [31:24] RESERVED 0x00 DISABLE_HLOCK_R [23] Control HLOCK for R-block (0: disable, 1: enable) RESERVED [22:16] RESERVED DISABLE_HLOCK_S [15] Control HLOCK for S-block (0: disable, 1:enable)
Page 82 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER Secure DMA control register REGISTER ADDRESS DESCRIPTION RESET VALUE SDMA_SEL 0x7E00_F110 Secure DMA input selection 0x0000_0000 SDMA_SEL DESCRIPTION RESET VALUE DMA selection for security Tx (always selects SDMA1 SECURITY_TX [31] regardless of SECURITY_TX field) DMA selection for security Rx (always selects SDMA1...
Page 83 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR Software reset control register REGISTER ADDRESS DESCRIPTION RESET VALUE SW_RST 0x7E00_F114 Generate software reset 0x0000_0000 SW_RST DESCRIPTION RESET VALUE RESERVED [31:16] RESERVED 0x0000 SWRESET [15:0] Generate software reset when the value is 0x6400 0x0000 Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 84 [7:0] Layout revision 0x02 Note: PRODUCT_ID register contains product information of S3C6400X. Although this is a read-only register, it must be written at least one time before reading. If it is read without writing operation, the read value is meaningless.
Page 85 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR Memory controller status register Memory controller status registers should be initialized by software except MEM_CFG_STAT. REGISTER ADDRESS DESCRIPTION RESET VALUE MEM_SYS_CFG 0x7E00_F120 Memory Subsystem configuration register 0x0000_0080 QOS_OVERRIDE0 0x7E00_F124 DMC0 QOS Override register 0x0000_0000 QOS_OVERRIDE1...
Page 86 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER SROMC - DMC0 - OneNANDC CS0 - OneNANDC CS1 – NFCON – CFCON Set usage of Xm1DATA[31:16] pins. 0 = Xm1DATA[31:16] pins are used for DMC1 upper halfword ADDR_EXPAND data field, data[31:16]. 1 = Xm1DATA[31:16] pins are used for SROMC upper 10-bit address field, address[25:16].
Page 87 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR QOS_OVERRIDE0 / DESCRIPTION RESET VALUE QOS_OVERRID1 RESERVED [31:16] RESERVED 0x0000_0000 Override Quality of Service for DMC0/DMC1. When one or more bits are high, and when the arid match bits in DMC0/DMC1 are equivalent to the QOS_OV_ID bits, then the quality of service of the read access is forced to minimum latency.
Page 88 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER 1 = NAND flash boot is set. Show with which area 0x00000000 address area is aliased. 00 = Stepping Stone in NFCON. CFG_BOOT_LOC [6:5] XOM dependent 01 = SROMC CS0 10 = OneNANDC CS0 11 = Internal ROM Show whether Xm1DATA[31:16] pins are used for SROMC address field or not.
Page 89 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR Power mode control register REGISTER ADDRESS DESCRIPTION RESET VALUE PWR_CFG 0x7E00_F804 Configure power manager 0x0000_0001 EINT_MASK 0x7E00_F808 Configure EINT mask 0x0000_0000 NORMAL_CFG 0x7E00_F810 Configure power manager at NORMAL mode 0xFFFF_FF00 STOP_CFG 0x7E00_F814 Configure power manager at STOP mode...
Page 90 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER BATF_WAKEUP_MASK field has 1) 11 : enter SLEEP mode or E-SLEEP mode Configure wakeup source after XnBATF is cleared CFG_BATF_WKUP 0: use nWRESET only 1: use all SLEEP wakeup source RESERVED DO NOT CHANGE Control 27MHz X-tal oscillator pad...
Page 91 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR When S3C6400 uses STOP mode, this field should be ETM_LOGIC [16] ‘1’. RESERVED [15:9] DO NOT CHANGE 0x00 0: LP mode(Retention), 1: active mode(ON), This field TOP_LOGIC must be ‘0’ before entering STOP mode. RESERVED...
Page 92 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER System stabilization counter REGISTER ADDRESS DESCRIPTION RESET VALUE OSC_FREQ 0x7E00_F820 Oscillator frequency scale counter 0x0000_000F OSC_STABLE 0x7E00_F824 Oscillation pad stable counter 0x0000_0001 PWR_STABLE 0x7E00_F828 Power stable counter 0x0000_0001 MTC_STABLE 0x7E00_F830 MTC stable counter 0xFFFF_FFFF OSC_FREQ...
Page 93 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR MTC_STABLE DESCRIPTION RESET VALUE RESERVED [31:28] RESERVED DOMAIN_ETM [27:24] Memory power stabilization counter for domain ETM DOMAIN_S [23:20] Memory power stabilization counter for domain S DOMAIN_F [19:16] Memory power stabilization counter for domain F DOMAIN_P...
Page 94 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER Others control register REGISTER ADDRESS DESCRIPTION RESET VALUE OTHERS 0x7E00_F900 Others control register 0x0000_801E OTHERS DESCRIPTION RESET VALUE RESERVED [31:17] RESERVED 0x0000 USB signal mask to prevent unwanted leakage. USB_SIG_MASK [16] (This bit must set before USB PHY is used.)
Page 95 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR Status register REGISTER ADDRESS DESCRIPTION RESET VALUE RST_STAT 0x7E00_F904 Reset status register 0x0000_0001 WAKEUP_STAT 0x7E00_F908 Wake-up status register 0x0000_0000 BLK_PWR_STAT 0x7E00_F90C Block power status register 0x0000_007F RST_STAT DESCRIPTION RESET VALUE RESERVED [31:6] RESERVED 0x0000_000 SW_RESET...
Page 96 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER BLK_PWR_STAT DESCRIPTION RESET VALUE RESERVED [31:7] RESERVED 0x0000_000 BLK_ETM Block ETM power ready BLK_S Block S power ready BLK_F Block F power ready BLK_P Block P power ready BLK_I Block I power ready BLK_V Block V power ready...
Page 97 SYSTEM CONTROLLER S3C6400X RISC MICROPROCESSOR Information register REGISTER ADDRESS DESCRIPTION RESET VALUE INFORM0 0x7E00_FA00 Information register 0 0x0000_0000 INFORM1 0x7E00_FA04 Information register 1 0x0000_0000 INFORM2 0x7E00_FA08 Information register 2 0x0000_0000 INFORM3 0x7E00_FA0C Information register 3 0x0000_0000 INFORMn DESCRIPTION RESET VALUE User defined information.
Page 98 S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER NOTE Preliminary product information describe products that are in development, 3-53 for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 99: Memory Subsystem
MEMORY SUBSYSTEM OVERVIEW The S3C6400X Memory Subsystem includes seven memory controllers, one SROM controller, two OneNAND controllers, one NAND Flash controller, one CF controller, and two DRAM controllers. Static memory controllers and 16-bit DRAM controller share memory port 0 by using EBI.
Page 100 MEMORY SUBSYSTEM S3C6400X RISC MICROPROCESSOR When NAND Flash or OneNAND is selected for boot device, nCS2 is used to access that boot media. EBI module supports AMBA AXI 3.0 low power interface (CSYSREQ, CACTIVE, and CSYSACK) to prevent memory controllers from accessing memories.
Page 101 S3C6400X RISC MICROPROCESSOR MEMORY SUBSYSTEM CFCON Compact 16-bit Flash Non-shared EBI4 control Control CS[7:0] Address[15:0] Decoder Data[15:0] NFCON Shared Control NAND EBI3 16-bit From Flash Non-shared System control Controller Control OneNAND0 EBI2 OneNAND 16-bit Port 0 Non-shared Control control Slave...
Page 102 MEMORY SUBSYSTEM S3C6400X RISC MICROPROCESSOR FUNCTIONAL DESCRIPTION The Memory Subsystem can be configured by System Controller. The memory configuration register name in System Controller is MEM_SYS_CFG. This address of this register is 0x7E00F120. System controller sends information as follows: Flash information...
Page 103 S3C6400X RISC MICROPROCESSOR MEMORY SUBSYSTEM Memory port 0 CS selection Set static memory chip selection multiplexing of memory port 0. Setting for MP0_CS_SEL[0] and MP0_CS_SEL[2] are ignored. Distinguishing OneNANDC and NFCON is done by XSELNAND pin value instead of MP0_CS_SEL[0] and MP0_CS_SEL[2].
Page 104 MEMORY SUBSYSTEM S3C6400X RISC MICROPROCESSOR Priority Type 0= Fixed priority / 1= Circular priority Fixed Priority Order CfgFixPriTyp[ 2:0] 0, 6~7 DMC0 SROMC OneNANDC OneNANDC NFCON CFCON DMC0 OneNANDC OneNANDC SROMC NFCON CFCON DMC0 OneNANDC NFCON SROMC OneNANDC CFCON DMC0...
Page 105 S3C6400X RISC MICROPROCESSOR MEMORY SUBSYSTEM EBI Interface The EBI, as a peripheral, relies on the memory controllers to release their external requests for the external bus when they are idle, because it has no other knowledge of when a transfer starts or completes.
Page 106 MEMORY SUBSYSTEM S3C6400X RISC MICROPROCESSOR EBICLK MEMCLK1 MEMCLK2 EBIREQ1 EBIGNT1 EBIBACKOFF1 EBIREQ2 EBIGNT2 EBIBACKOFF2 Figure 4-4. EBIBACKOFF signal Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 107 S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER DRAM CONTROLLER OVERVIEW DRAM Controller is from ARM PrimeCell CP003 AXI Dynamic Memory Controller (PL340) based on ARM PrimeCell CP003 AXI DMC (PL340). Original AMBA APB 3.0 port for programming configuration registers is covered by using AxiToApb bridge component, which implements an AXI slave port connected to an APB master port.
Page 108 DRAM CONTROLLER S3C6400X RISC MICROPROCESSOR Supports 2 outstanding exclusive access transfers. Configurable memory access timing by using SFRs. Support extended MRS (EMRS) set. For Memory Port 1, CKE can be controlled separately. For Memory Port 1, Not supports 16bit SDR SDRAM, mobile SDR SDRAM...
Page 109 S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER SDRAM MEMORY INTERFACE DRAM Controller supports up to two chips of same type and can assign a maximum of 256 MByte address space per chip. All chips in the same port share all pins, except clock enable signals and chip select signals. An example of DDR SDRAM memory interface connection is shown in figure 5-2.
Page 110 DRAM CONTROLLER S3C6400X RISC MICROPROCESSOR SDRAM INITIALIZATION SEQUENCE On power-on reset, software must initialize the DRAM controller and each of the SDRAM connected to the DRAM controller. Refer to the SDRAM data sheet for the start up procedure. Example sequences are given below.
Page 111 S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER command. Program mem_cmd in direct_cmd to ‘2’b11’, which makes DRAM Controller issue ‘Autorefresh’ memory command. Program mem_cmd in direct_cmd to ‘2’b00’, which makes DRAM Controller issue ‘Prechargeall’ memory command. Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 112 11 = 4 chips Memory chips [8:7] However, S3C6400X uses only two chip select signals per DRAM controller. The type of SDRAM that DRAM controller supports: 100 = Support SDR SDRAM (normal or mobile) and DDR SDRAM...
Page 113 S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER Changes the state of the DRAM controller Memc_cmd [2:0] 000 = Go 001 = Sleep 010 = Wakeup 011 = Pause 100 = Configure 101~111 = Reserved DIRECT COMMAND REGISTER Register Address Description Reset Value...
Page 114 DRAM CONTROLLER S3C6400X RISC MICROPROCESSOR Enables the refresh command generation for the number of memory chips. It is only possible to generate commands up to and including the number of chips in the configuration defined in the DRAM controller status register:...
Page 115 S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER Encodes the number of bits of the AXI address that comprise the row address: 000 = 11 bits 001 = 12 bits 010 = 13 bits Row bits [5:3] 011 = 14 bits 100 = 15 bits...
Page 116 DRAM CONTROLLER S3C6400X RISC MICROPROCESSOR Encodes whether the CAS latency is half a memory clock cycle more than the value given in bits[3:1] CAS Half cycle 0 = Zero cycle offset to value in [3:1]. [0] is forced to 0 in MDDR and SDR mode.
Page 117 S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER T_RC REGISTER Register Address Description Reset Value P0T_RC 0x7E000024 16-bit DRAM controller t_RC register P1T_RC 0x7E001024 32-bit DRAM controller t_RC register PnT_RC Description Initial State [31:4] Read undefined. Write as Zero t_RC [3:0] Set Active bank x to Active bank x delay in memory clock cycles.
Page 118 DRAM CONTROLLER S3C6400X RISC MICROPROCESSOR PnT_RP Description Initial State [31:6] Read undefined. Write as Zero scheduled_RP [5:3] Set the precharge to RAS delay in aclk cycles -3. t_RP [2:0] Set the precharge to RAS delay in memory clock cycles T_RRD REGISTER...
Page 119 S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER T_XP REGISTER Register Address Description Reset Value P0T_XP 0x7E000040 16-bit DRAM controller t_XP register 0x01 P1T_XP 0x7E001040 32-bit DRAM controller t_XP register 0x01 PnT_XP Description Initial State [31:8] Read undefined. Write as Zero t_XP [7:0] Set the exit power down command time in memory clock cycles.
Page 120 01 = AXI clock and memory clock are synchronous, and AXI clock is the same frequency or slower than memory clock. Clock config [1:0] S3C6400X supports synchronous configuration. If this value is set to asynchronous, S3C6400X should endure performance degradation. 10~11 = reserved...
Page 121 S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER Pn_id_<n>_cfg Description Initial State [31:10] Read undefined. Write as Zero QoS_MAX [9:2] Set a maximum quality of service. 0x00 QoS_MIN Set a minimum quality of service. Enables a quality of service value to be applied to memory reads QoS_Enable from address ID <n>.
Page 122 DRAM CONTROLLER S3C6400X RISC MICROPROCESSOR USER_CONFIG REGISTER Register Address Description Reset Value P0_user_cfg 0x7E000304 16-bit DRAM controller user_cfg register 0x00 P1_user_cfg 0x7E001304 32-bit DRAM controller user_cfg register 0x00 Pn_user_cfg Description Initial State [31:8] Read undefined. Write as Zero DQS[3] delay [7:6] Selects input dqs[3] delay.
Page 123 S3C6400X RISC MICROPROCESSOR SROM CONTROLLER SROM CONTROLLER OVERVIEW The S3C6400 SROM Controller (SROMC) supports external 8, 16-bit NOR Flash, PROM, SRAM memory. From now on, we refer to controller as SROM Controller. S3C6400 SROM Controller supports 6-bank memory of maximum 128 MB size only.
Page 124 SROM CONTROLLER S3C6400X RISC MICROPROCESSOR BLOCK DIAGRAM AHB I/F for SROM SFR SROM SROM I/F CONTROL & SINGAL SROM MEM I/F STATE MACHINE DECODER GENERATER AHB I/F for SROM MEM DATA PATH Figure 6-1 SROM Controller Block Diagram SROM CONTROLLER FUNCTION DESCRIPTION SROM Controller support SROM interface for Bank0 to Bank5.
Page 125 S3C6400X RISC MICROPROCESSOR SROM CONTROLLER nWAIT PIN OPERATION If the WAIT operation corresponding to each memory bank is enabled, the nOE duration will be prolonged by the external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the next clock after sampling nWAIT is high.
Page 126 SROM CONTROLLER S3C6400X RISC MICROPROCESSOR PROGRAMMABLE ACCESS CYCLE HCLK ADDR ADDRESS 0 ADDRESS 1 Tcah Tacs nGCS Tcoh Tcos Tacc Tacp DATA(R) DATA 0 DATA 1 Tacs = 2-cycle Tacp = 2-cycle Tcos = 2-cycle Tcoh = 2-cycle Tacc = 3-cycle...
Page 127 S3C6400X RISC MICROPROCESSOR SROM CONTROLLER SPECIAL FUNCTION REGISTERS SROM BUS WIDTH & WAIT CONTRL REGISTER(SROM_BW) Register Address Description Reset Value SROM_BW 0x70000000 SROM Bus width & wait control 0x0000_000x SROM_BW Description Initial State Reserved [31:24] Reserved ByteEnable5 [23] nWBE / nBE(for UB/LB) control for Memory Bank5...
Page 128 SROM CONTROLLER S3C6400X RISC MICROPROCESSOR DataWidth2 Data bus width control for Memory Bank2 0 = 8-bit 1 = 16-bit ByteEnable1 nWBE / nBE(for UB/LB) control for Memory Bank1 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using...
Page 129 S3C6400X RISC MICROPROCESSOR SROM CONTROLLER SROM BANK CONTROL REGISTER (SROM_BC : XrCSn0 ~ XrCSn2) Register Address Description Reset Value SROM Bank0 control register SROM_BC0 0x70000004 0x000F_0000 SROM Bank1 control register SROM_BC1 0x70000008 0x000F_0000 SROM Bank2 control register SROM_BC2 0x7000000C 0x000F_0000...
Page 130 SROM CONTROLLER S3C6400X RISC MICROPROCESSOR 1110 = 14 clocks 1111 = 15 clocks [3:2] Reserved Reserved [1:0] Page mode configuration 00 = normal (1 data) 01 = 4 data 10 = 8 data 11 = 16 data Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 131 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER ONENAND CONTROLLER This chapter describes the functions and usage of OneNAND controller in S3C6400X RSIC microprocessor. OVERVIEW S3C6400X supports external 16-bit bus for both asynchronous and synchronous OneNAND external memory via shared memory port 0. It supports maximum 2 banks by using two controllers. The OneNAND Controller is an Advanced Microcontroller Bus Architecture (AMBA 2) compliant System-on-Chip peripheral.
Page 132 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR BLOCK DIAGRAM Figure 7-1 OneNAND Controller Block Diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 133 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER SIGNAL DESCRIPTION External Memory Interface Signal Description Xm0DATA[15:0] (Data Bus) outputs address during memory read/write address Xm0DATA phase, inputs data during memory read data phase and outputs data during [15:0] memory write data phase. Xm0CSn[1:0] (Chip Select) are activated when the address of a memory is within the address region of each bank.
Page 134 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR INPUT CLOCKS The OneNAND controller has three clock source inputs. Bus system interface gets AHB bus clock, HCLK. Flash controller core gets two flash clocks, mclk and mclk_flash. Frequency of mclk must be double of mclk_flash, which is supplied to OneNAND flash memory.
Page 135 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER COMMAND MAPPING There are four kinds of commands supported by the OneNand flash memory controller. These commands are selected through the value of bits 23 and 22 of the incoming address. The command mapping determines the way in which the lower 22 bits of the address will be used.
Page 136 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR Table 7-3 Map 01 Address Mapping Address Name Description Bits 31:24 AHB_int_add AHB Port Address 23:22 CMD_MAP 01 = Read or Write to the Memory Device 21:0 MEM_ADDR Refer table 7-1. • “ 10” = Map 10 Commands.
Page 137 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER FSA are 1 = Erase is in progress. unused for Write 0x01 Save the block address for a multi-block erase. This does NOT initiate the Erase erase. Operations and must Write 0x03 Save the block address for a single-block erase and initiate the erase. Also be cleared.
Page 138 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR Copy Back Operations The OneNand flash controller supports copy operations. However, the memory device may have limited support for this function. If the copy back function is not supported, an interrupt will be triggered. An interrupt will also be triggered if the source block is not set before the destination block is specified, or if the destination block is not specified in the next command following a source block specification.
Page 139 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER - Verify Read Operations Multi-block erases must be verified through a verify read command. This command operates serially and verifies one block at a time. Each block of the multi-block erase must be verified! An interrupt (Ers_Fail) will be triggered if the block does not verify.
Page 140 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR - Read/Modify/Write Operations The user may need to read a specific page or modify a few words, bytes or bits in a page. The read/modify/write operations are used for this purpose. A read command pulls the desired data from memory to a buffer. The user will then modify the information in the buffer and then issue another command to write that information back to memory.
Page 141 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER PIPELINE READ/WRITE AHEAD COMMAND When a pipeline read-ahead or write-ahead command is received, and the controller is idle, this command will initiate a load operation immediately into one of the dataram buffers of the memory device. Note that the read- ahead command does NOT return the data to the AHB interface, and the write-ahead command does NOT write data to the flash address.
Page 142 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR • Set Up a Single Area for Pipelined Write-Ahead The procedure to set up an area for pipelined write-ahead is as follows: 1. You must set the CMD_MAP to “Map 10" and set the starting address of the block to pre-write in the FBA, FPA and FSA of the address.
Page 143 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER • Set Up Multiple Areas for Pipelined Write-Ahead The procedure to set up multiple areas for pipelined write-ahead is as follows: 1. You must set the CMD_MAP to “Map 10" and set the starting address of the first block to pre-write in the FBA, FPA and FSA of the address.
Page 144 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR CONTROLLER USAGE EXCEPTION The OneNAND controller is designed with following exceptions: 1. The OneNAND Flash Memory Controller does not enforce any timing restrictions around the use of the reset register. 2. The burst length value of OneNAND controller must be programmed with the same to or less than the burst length value of the OneNAND flash device.
Page 145 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER BOOT WITH ONENAND CONTROLLER The OneNAND controller supports OneNAND boot with following steps: 1. External reset is de-asserted. 2. System controller generates global reset. 3. OneNAND controller starts counting “FLASH_COLD_RST_DELAY” with core clock. 4. After ARM Core reset is de-asserted, Instruction fetch is started, but this fetch is suspended by OneNAND controller.
Page 146 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR REGISTER DESCRIPTION MEMORY MAP Register Address Description Reset Value MEM_CFG0 0x70100000 R/W Bank0 Memory Device Configuration Register 0x0000 BURST_LEN0 0x70100010 R/W Bank0 Burst Length Register 0x0000 MEM_RESET0 0x70100020 R/W Bank0 Memory Reset Register 0x0000 INT_ERR_STAT0...
Page 147 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER Register Address Description Reset Value MEM_CFG1 0x70180000 R/W Bank1 Memory Device Configuration Register 0x0000 BURST_LEN1 0x70180010 R/W Bank1 Burst Length Register 0x0000 MEM_RESET1 0x70180020 R/W Bank1 Memory Reset Register 0x0000 INT_ERR_STAT1 0x70180030 R/W Bank1 Interrupt Error Status Register...
Page 148 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR Individual Register Descriptions MEMORY DEVICE CONFIGURATION REGISTER The value programmed will depend on the actual memory device being used. This value is related with system configuration register 1(0xF221) of OneNAND Flash. This data is used to configure the flash for the hardware and software environment and may include burst length, read latency, transfer mode, ECC configuration, polarity levels, etc.
Page 149 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER • 1 = High for ready. INTPOL INT signal polarity. • 0 = Low for interrupt pending. • 1 = High for interrupt pending. IOBE I/O Buffer enable for INT and RDY signals, INT and RDY outputs are hi-Z at start up, bit 7 and 6 become valid after IOBE is set to 1.
Page 150 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR 4: Supports SINGLE and INCR4. 8: Supports SINGLE and INCR4. 16: Supports SINGLE, INCR4 and INCR8. Others: Reserved MEMORY RESET REGISTER Register Address Description Reset Value MEM_RESET0 0x70100020 R/W Bank0 Memory Reset Register 0x0000 MEM_RESET1...
Page 151 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER BLK_RW_CMP The block read or writes transfer has been completed. This interrupt relates to “verify read” and “pipeline read-ahead” commands. ERS_CMP The erase operation has been completed. This interrupt is automatically reset at the beginning of an erase operation.
Page 152 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR INTERRUPT ERROR ACKNOWLEDGE REGISTER Register Address Description Reset Value INT_ERR_ACK0 0x70100050 Bank0 Interrupt Error Acknowledge Register 0x0000 INT_ERR_ACK1 0x70180050 INT_ERR_ACKn Description Initial State Reserved [31:14] CACHE_OP_ERR [13] Acknowledge bits that correspond to the bits in the INT_ERR_STAT register.
Page 153 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER MANUFACTURER ID REGISTER Register Address Description Reset Value MANUFACT_ID0 0x70100070 Bank0 Manufacturer ID Register Memory dependent MANUFACT_ID1 0x70180070 MANUFACT_IDn Description Initial State Reserved [31:16] MANUFACT_ID [15:0] The value programmed will depend on the actual memory device being used.
Page 154 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR 00 = 1.8V 01/10/11 = reserved. DATA BUFFER SIZE REGISTER Register Address Description Reset Value DATA_BUF_SIZE0 0x70100090 Bank0 Data Buffer Size Register Memory dependent DATA_BUF_SIZE1 0x70180090 DATA_BUF_SIZEn Description Initial State Reserved [31:16] DATA_BUF [15:0] The value programmed will depend on the actual memory device being used.
Page 155 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER TECHNOLOGY REGISTER Register Address Description Reset Value TECH0 0x701000C0 Bank0 Technology Register Memory dependent TECH1 0x701800C0 TECHn Description Initial State Reserved [31:16] TECHNOLOGY [15:0] The value programmed will depend on the actual memory device being used. This register is set by the flash controller after reset.
Page 156 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR FSA WIDTH REGISTER Register Address Description Reset Value FSA_WIDTH0 0x701000F0 R/W Bank0 FSA Width Register 0x0002 FSA_WIDTH1 0x701800F0 FSA_WIDTHn Description Initial State Reserved [31:3] [2:0] Sets the number of bits that will be used to represent the number of sectors.
Page 157 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER DATARAM1 CODE REGISTER Register Address Description Reset Value DATARAM10 0x70100120 R/W Bank0 Dataram1 Code Register 0x0003 DATARAM11 0x70180120 DATARAM1n Description Initial State Reserved [31:4] DATARAM1 [3:0] Sets the non-sector part of the data for ram1. Default value is 0x3.
Page 158 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR TSRF On all read or write commands through map 01, if this bit is set, the data in the spare area of memory will be transferred to the asynchronous FIFO of the memory controller along with the main data.
Page 159 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER ERROR PAGE ADDRESS REGISTER Register Address Description Reset Value ERR_PAGE_ADDR0 0x70100180 Bank0 Error Page Address Register 0x0000 ERR_PAGE_ADDR1 0x70180180 ERR_PAGE_ADDRn Description Initial State Reserved [31:6] FAIL_PAGE_ADDR [5:0] After a program, load or erase error interrupt, this register will hold the page address of the failing operation.
Page 160 ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR INTERRUPT MONITOR CYCLE REGISTER Register Address Description Reset Value INT_MON_CYC0 0x701001B0 R/W Bank0 Interrupt Monitor Cycle Count Register 0x01F4 INT_MON_CYC1 0x701801B0 INT_MON_CYCn Description Initial State Reserved [31:12] INT_MON_CYC [11:0] Sets the number of cycles in between checks of the INT_ERR_STAT register and the memory device’s status...
Page 161 S3C6400X RISC MICROPROCESSOR ONENAND CONTROLLER ERROR BLOCK ADDRESS REGISTER Register Address Description Reset Value ERR_BLK_ADDR0 0x701001E0 Bank0 Error Block Address Register 0x0000 ERR_BLK_ADDR1 0x701801E0 ERR_BLK_ADDRn Description Initial State Reserved [31:12] FAIL_BLK_ADDR [11:0] After a program, load or erase error interrupt, this register will hold the block address of the failing operation.
Page 162 SDRAM. S3C6400X boot code can be executed on an external NAND flash memory. The S3C6400X is equipped with an internal SRAM buffer called ‘Steppingstone’. This supports NAND flash boot loader. When you boot, first 4 KB of the NAND flash memory will be loaded into Steppingstone and the boot code that is loaded into Steppingstone will be executed.
Page 163 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR BLOCK DIAGRAM nFCE ECC Gen. NAND FLASH Interface Control & R/nB State Machine I/O0 - I/O7 Slave I/F Stepping Stone Stepping Stone Controller (4KB SRAM) Figure 8-1 NAND Flash Controller Block Diagram BOOT LOADER FUNCTION...
Page 164 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER PIN CONFIGURATION TABLE OM[4:0] AdvFlash PageSize AddrCycle BusWidth 0000x 0: Normal NAND 1: 512-byte 0: 3 cycle 0: 8-bit data bus 0001x 0: Normal NAND 1: 512-byte 1: 4 cycle 0: 8-bit data bus...
Page 165 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR NAND FLASH MEMORY TIMING TACLS TWRPH0 TWRPH1 HCLK CLE / ALE DATA COMMAND / ADDRESS Figure 8-3. CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) Block Diagram TWRPH0 TWRPH1 HCLK nWE / nRE DATA DATA Figure 8-4 nWE &...
Page 166 NAND FLASH CONTROLLER SOFTWARE MODE S3C6400X only supports software mode access. Use this mode to access NAND flash memory completely. The NAND Flash Controller supports direct access interface with the NAND flash memory. 1) Writing to the command register = the NAND Flash Memory command cycle...
Page 167 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR Data Register Configuration 1) 8-bit NAND Flash Memory Interface Word Access Register Endian Bit [31:24] Bit [23:16] Bit [15:8] Bit [7:0] NFDATA Little I/O[ 7:0] I/O[ 7:0] I/O[ 7:0] I/O[ 7:0] Half-word Access Register...
Page 168 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER SLC / MLC ECC (Error Correction Code) NAND flash controller has four ECC (Error Correction Code) modules for SLC NAND flash memory and one ECC module for MLC NAND flash memory. For SLC NAND flash memory interface, NAND flash controller consists of 4 ECC modules. The SLC ECC modules can be used for (up to) 2048 bytes ECC parity code generation, and the other can be used for (up to) 4 bytes ECC Parity code generation.
Page 169 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR ECC MODULE FEATURES ECC generation is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit of the Control register. When ECCLock is Low, ECC codes are generated by the H/W ECC modules. SLC ECC Register Configuration Following tables shows the configuration of SLC ECC value read from spare area of external NAND flash memory.
Page 170 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER SLC ECC PROGRAMMING GUIDE 1) To use SLC ECC in software mode, reset the ECCType to ‘0’ (enable SLC ECC)‘. ECC module generates ECC parity code for all read / write data when MainECCLock (NFCON[7]) and SpareECCLock (NFCON[6]) are unlocked(‘0’).
Page 171 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR ECCType to ‘1’(enable MLC ECC). ECC module generates ECC parity code for 24-byte write data. So you have to reset ECC value by writing the InitMECC (NFCONT[5]) bit as ‘1’ and have to clear the MainECCLock (NFCONT[7]) bit to ‘0’(Unlock) before write data.
Page 172 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER NAND FLASH MEMORY MAPPING OM[4:3] = 01/10/11 OM[4:3] = 00 0x40000_0000 SROM/CF SROM/CF 2MB/4MB/8MB/16MB (Xm0CSn[5]) (Xm0CSn[5]) /32MB/64MB/128MB Refer to 0x3800_0000 Table 5-1 2MB/4MB/8MB/16MB SROM/CF SROM/CF /32MB/64MB/128MB (Xm0CSn[4]) (Xm0CSn[4]) 0x3000_0000 SROM/OneNAND/NAND SROM/OneNAND/NAND 128MB (Xm0CSn[3]) (Xm0CSn[3])
Page 173 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR NAND FLASH MEMORY CONFIGURATION Figure 8-6 A 8-bit NAND Flash Memory Interface Block Diagram Note: NAND CONTROLLER can support to control two nand flash memories . NAND BOOT Other BOOT Xm0CSn[2] NAND CONTROLLER CS0...
Page 174 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER NAND FLASH CONTROLLER SPECIAL REGISTERS NAND FLASH CONTROLLER REGISTER MAP Address Reset value Name Description Base + 0x00 0x0000100X NFCONF Configuration register Base + 0x04 0x000100C6 NFCONT Control register Base + 0x08 0x00 NFCMMD...
Page 175 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR Nand Flash configuration Register Register Address Description Reset Value NFCONF 0x70200000 NAND Flash Configuration register 0x0000100X NFCONF Description Initial State NANDBoot [31] Read Only. Shows whether NAND boot or not 1=NAND Flash memory boot...
Page 176 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER 0: 4 address cycle 1: 5 address cycle This bit is determined by OM[1] pin status during reset and wake-up from sleep mode. This bit can be changed by software. Reserved Reserved. Must be written 0.
Page 177 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR CONTROL REGISTER Register Address Description Reset Value NFCONT 0x70200004 NAND Flash control register 0x000100C6 NFCONT Description Initial State Reserved [31:19] Reserved ECC Direction [18] 4-bit ECC encoding / decoding control 0: Decoding 4-bit ECC, It is used for page read...
Page 178 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER program or erase locking area (the area setting in NFSBLK (0x70200020) to NFEBLK (0x70200024)- 1). EnbRnBINT RnB status input signal transition interrupt control 0: Disable RnB interrupt 1: Enable RnB interrupt RnB_TransMode RnB transition detection configuration...
Page 179 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR COMMAND REGISTER Register Address Description Reset Value NFCMMD 0x70200008 NAND Flash command set register 0x00 NFCMMD Description Initial State Reserved [31:8] Reserved 0x00 NFCMMD [7:0] NAND Flash memory command value 0x00 ADDRESS REGISTER Register...
Page 180 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER MAIN DATA AREA ECC REGISTER Register Address Description Reset Value NFMECCD0 0x70200014 NAND Flash ECC 1 register for main area data read 0x00000000 (Note) Refer to ECC MODULE FEATURES. NFMECCD1 0x70200018 NAND Flash ECC 3...
Page 181 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR PROGRMMABLE BLOCK ADDRESS REGISTER Register Address Description Reset Value NFSBLK 0x70200020 NAND Flash programmable start block address 0x000000 NFEBLK 0x70200024 NAND Flash programmable end block address 0x000000 Nand Flash can be programmed between start and end address.
Page 182 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER The NFSLK and NFEBLK can be changed while Soft lock bit(NFCONT[16]) is enabled. But cannot be changed when Lock-tight bit(NFCONT[17]) is set. NAND flash memory When NFSBLK=NFEBLK Address Locked area High (Read only) NFEBLK...
Page 183 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR NFCON STATUS REGISTER Register Address Description Reset Value NFSTAT 0x70200028 R/W NAND Flash operation status register 0x0080001D NFSTAT Description Initial State Reserved [31:24] 0x00 Read undefined BootDone [23] When NAND Flash is set as booting device, it indicates whether loading boot area to Stepping stone is finished or not.
Page 184 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER ECC0/1 ERROR STATUS REGISTER Register Address Description Reset Value NFECCERR0 0x7020002C NAND Flash ECC Error Status register for I/O [7:0] 0x007FFFFA NFECCERR1 0x70200030 NAND Flash ECC Error Status register for I/O [7:0] 0x007FFFFA When ECCType is SLC.
Page 185 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR When ECCType is MLC. NFECCERR0 Description Initial State ECC Busy [31] Indicates the 4-bit ECC decoding engine is searching whether a error exists or not 0: Idle 1: Busy ECC Ready [30] ECC Ready bit...
Page 186 S3C6400X RISC MICROPROCESSOR NAND FLASH CONTROLLER MAIN DATA AREA ECC0 STATUS REGISTER Register Address Description Reset Value NFMECC0 0x70200034 SLC or MLC NAND Flash ECC status register 0xXXXXXX NFMECC1 0x70200038 MLC NAND Flash ECC status register 0xXXXXXX When ECCType is SLC...
Page 187 NAND FLASH CONTROLLER S3C6400X RISC MICROPROCESSOR SPARE AREA ECC STATUS REGISTER Register Address Description Reset Value NFSECC 0x7020003C NAND Flash ECC register for I/O [7:0] 0xXXXXXX NFSECC Description Initial State Reserved [31:16] Reserved 0xXXXX SECC0_1 [15:8] Spare area ECC1 Status for I/O[7:0]...
Page 188 S3C6400X RISC MICROPROCESSOR CF CONTROLLER CF CONTROLLER This chapter describes the functions and usage of CF Controller in S3C6400X RISC microprocessor. OVERVIEW CF controller supports both PC card memory/IO mode & True-IDE mode. CF controller is compatible with CF standard spec. R3.0.
Page 189 CF CONTROLLER S3C6400X RISC MICROPROCESSOR The ATAPI controller features: The ATAPI controller is compatible with the ATA/ATAPI-6 standard. The ATAPI controller has 30 word-sized (32bits) Special Function Registers. The ATAPI controller has 1 FIFO that is 16 x 32bit. The ATAPI controller has internal DMA controller (from ATA device to memory or from memory to ATA device).
Page 190 S3C6400X RISC MICROPROCESSOR CF CONTROLLER I/O DESCRIPTION Direct mode Indirect mode (UDMA mode Description only) XhiCSn Card enable strobe Xm0CSn[4] PC card mode : lower byte enable strobe XhiADR[8] True-IDE mode : chip selection (nCS0) XhiCSn_main Card enable strobe Xm0CSn[5]...
Page 191 CF CONTROLLER S3C6400X RISC MICROPROCESSOR XmmcCMD0 XmmcCMD1 XmmcDATA1[5] XhiADR[1] XuRTSn[1] XEINT[10] XspiMOSI[0] XpcmFSYNC[0] XmmcDATA0[0] XmmcDATA1[0] XmmcDATA1[6] XhiADR[2] XuRXD[3] Xm0DATA[15:0] XhiDATA[0] CF data bus XhiDATA[1] XhiDATA[2] XhiDATA[3] XhiDATA[4] XhiDATA[5] XhiDATA[6] XhiDATA[7] XhiDATA[8] (XhiDATA[16]) XhiDATA[9] (XhiDATA[17]) XhiDATA[10] (XhiCSn) XhiDATA[11] (XhiCSn_main) XhiDATA[12] (XhiCSn_sub)
Page 192 S3C6400X RISC MICROPROCESSOR CF CONTROLLER XhiDATA[15] (XhiIRQn) Xm0CData Xm0CData Card detect signals Interrupt request from CF card. PC card mode : active low (memory mode : level triggering, Xm0INTata Xm0INTata I/O mode : edge triggering) True-IDE mode : active high...
Page 193 CF CONTROLLER S3C6400X RISC MICROPROCESSOR BLOCK DIAGRAM TOP-LEVEL BLOCK DIAGRAM A top-level block diagram of the overall CF controller is shown below in Figure 9-1. CF controller AHB master IF ATAPI controller CF card AHB slave IF PC card controller...
Page 194 S3C6400X RISC MICROPROCESSOR CF CONTROLLER PC CARD CONTROLLER BLOCK DIAGRAM A top-level block diagram of the PC card controller is shown below in Figure 9-2. PC card controller Block ADDR nIOWR nIORD Main nREG Controller AHB ADDR & WDATA Data...
Page 195 CF CONTROLLER S3C6400X RISC MICROPROCESSOR ATAPI CONTROLLER BLOCK DIAGRAM A top-level block diagram of the ATAPI controller is shown below in Figure 9-3. ATAPI controller Block PIO data AHB slave IF Slave control/interrupt interface ATA interface ATAPI ATA write data...
Page 196 S3C6400X RISC MICROPROCESSOR CF CONTROLLER TIMING DIAGRAM PC CARD MODE nCE1 nCE2 IORD IOWR IDLE SET UP COMMAND HOLD IDLE Figure 9-4: PC Card State Definition Area Attribute memory I/O interface Common memory (min, Max) nS Set up (30, --)
Page 197 CF CONTROLLER S3C6400X RISC MICROPROCESSOR TRUE-IDE MODE PIO Mode PIO Mode Waveform CS0,CS1, DA[2:0] teoc DIOR-/ DIOW- DD[15:0] or DD[7:0] DD[15:0] or DD[7:0] Figure 9-5: PIO Mode Waveform Timing Parameter In PIO Mode PIO mode PIO 0 PIO 1 PIO 2...
Page 198 S3C6400X RISC MICROPROCESSOR CF CONTROLLER UDMA Mode Direct mode and Indirect mode Host can control device through EBI in indirect mode. If the IO voltage of external memory is not 3.3V, level shifter is required for data bus. Level shifter requires a direction control bit for data bus. Two pins, XhiIRQn or XirSDBW, can be selected for a direction control bit.
Page 199 CF CONTROLLER S3C6400X RISC MICROPROCESSOR UDMA-Out Transfer (termination by device) DMARQ DMACK tACKENV tACKENV DIOW DIOR tACKENV CS0,CS1, DA[2:0] IORDY tDVS tDVH tDVS tDVH DD[15:0 ] or DD[7:0] tACKENV Figure 9-8: UDMA - Out Operation (terminated by device) UDMA-Out Transfer (termination by host)
Page 200 S3C6400X RISC MICROPROCESSOR CF CONTROLLER UDMA mode UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4 tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55) (160, --) (125, --) (100, --) (100, --) (100, --) (50, --)
Page 201 CF CONTROLLER S3C6400X RISC MICROPROCESSOR SPECIAL FUNCTION REGISTERS MEMORY MAP Memory Map Diagram(HSEL_SLV_Base = 0x7030_0000) SFR Area SFR_Base = HSEL_SLV_Base + 0x1800 Common Memory Area HSEL_SLV_Base + 0x1000 I/O Area HSEL_SLV_Base + 0x0800 Attribute Memory Area HSEL_SLV_Base + 0x0000 Reserved Area...
Page 202: Table Of Contents
S3C6400X RISC MICROPROCESSOR CF CONTROLLER Register address Table Register Address Description Reset Value SFR_BASE 0x70301800 CF card host controller base address MUX_REG 0x70301800 Top level control & configuration register 0x00000006 Reserved ~ 0x001C Reserved area PCCARD_BASE 0x70301820 PC card controller base address...
Page 203 CF CONTROLLER S3C6400X RISC MICROPROCESSOR ATA_PIO_SCR 0x7030195C ATA PIO sector count register 0x00000000 ATA_PIO_LLR 0x70301960 ATA PIO device LBA low register 0x00000000 ATA_PIO_LMR 0x70301964 ATA PIO device LBA middle register 0x00000000 ATA_PIO_LHR 0x70301968 ATA PIO device LBA high register 0x00000000...
Page 204 S3C6400X RISC MICROPROCESSOR CF CONTROLLER PCCARD_CNFG&STATUS Register Address Description Reset Value PCCARD_CNFG&ST PCCARD_CNFG&STATUS is used to set the 0x70301820 0x0000_0F07 ATUS configuration & read the status of card. PCCARD_CNFG&ST Bits Description Reset ATUS Value Reserved [31:14] Reserved bits CARD_RESET [13]...
Page 205 CF CONTROLLER S3C6400X RISC MICROPROCESSOR PCCARD_INTMSK&SRC Register Address Description Reset Value PCCARD_INTMS PCCARD_INTMSK&SRC is interrupt source & 0x70301824 0x0000_0700 K&SRC interrupt mask register. PCCARD_INTMS Bits Description Reset K&SRC Value Reserved [31:11] Reserved bits INTMSK_ERR_N [10] Interrupt mask bit of no card error...
Page 206: Pccard_Attr
S3C6400X RISC MICROPROCESSOR CF CONTROLLER PCCARD_ATTR Register Address Description Reset Value PCCARD_ATTR is used to set the card access PCCARD_ATTR 0x70301828 0x0003_1909 timing. PCCARD_ATTR Bits Description Reset Value Reserved [31:23] Reserved bits HOLD_ATTR [22:16]] Hold state timing of attribute memory area...
Page 207: Pccard_Comm
CF CONTROLLER S3C6400X RISC MICROPROCESSOR PCCARD_COMM Register Address Description Reset Value PCCARD_COMM is used to set the card access PCCARD_COMM 0x70301830 0x0003_1909 timing. PCCARD_COMM Bits Description Reset Value Reserved [31:23] Reserved bits HOLD_COMM [22:16]] Hold state timing of common memory area...
Page 208: Ata_Control
S3C6400X RISC MICROPROCESSOR CF CONTROLLER ATA_CONTROL Register Address Description Reset Value ATA_CONTROL 0x70301900 ATA enable and clock down status 0x0000_0002 ATA_CONTROL Bits Description Reset Value Reserved [31:2] Reserved bits CLK_DOWN_READY Status for clock down This bit is asserted in idle state when ATA_CONTROL bit [0] is zero.
Page 209 CF CONTROLLER S3C6400X RISC MICROPROCESSOR ATA_COMMAND Register Address Description Reset Value ATA_COMMAND 0x70301908 ATA command 0x0000_0000 ATA_COMMAND Bits Description Reset Value Reserved [31:2] Reserved bits XFR_COMMAND [1:0] ATA transfer command Four command types (START, STOP, ABORT and CONTINUE) are supported for data transfer control.
Page 210: Ata_Status
S3C6400X RISC MICROPROCESSOR CF CONTROLLER ATA_SWRST Register Address Description Reset Value ATA_SWRST 0x7030190C ATA software reset 0x0000_0000 ATA_SWRST Bits Description Reset Value Reserved [31:1] Reserved bits ATA_SWRSTN Software reset for the ATAPI host 0: No reset 1: Software reset for all ATAPI host module.
Page 211: Ata_Irq_Mask
CF CONTROLLER S3C6400X RISC MICROPROCESSOR ATA_IRQ_MASK Register Address Description Reset Value ATA_IRQ_MASK 0x70301914 ATA interrupt mask 0x0000_001F ATA_IRQ_MASK Bits Description R/W Reset Value Reserved [31:2] Reserved bits MASK_SBUT_EMPTY_INT Interrupt mask bit of source buffer empty 0 : unmask 1 : mask...
Page 212 S3C6400X RISC MICROPROCESSOR CF CONTROLLER ATA_CFG Register Address Description Reset Value ATA_CFG 0x70301918 ATA configuration for ATA interface 0x0000_0000 ATA_CFG Bits Description Reset Value Reserved [31:10] Reserved bits UDMA_AUTO_M Determines whether to continue automatically in case of early termination in UDMA mode by Device. This bit must not be changed during runtime operation.
Page 213: Ata_Cfg
CF CONTROLLER S3C6400X RISC MICROPROCESSOR ATA_CFG Bits Description Reset Value BYTE_SWAP Determines whether data endian is little or big in 16bit data. 0 : little endian ( data[15:8], data[7:0] ) 1 : big endian ( data[7:0], data[15:8] ) ATADEV_IRQ_AL Device interrupt signal level...
Page 214: Ata_Udma_Time
S3C6400X RISC MICROPROCESSOR CF CONTROLLER ATA_UDMA_TIME Register Address Description Reset Value ATA_UDMA_TIME 0x70301930 ATA UDMA timing 0x020b_1362 ATA_UDMA_TIME Bits Description Reset Value Reserved [31:28] Reserved bits UDMA_TDVH [27:24] UDMA timing parameter tDVH tDVH = HCLK time * (UDMA_TDVH + 1)
Page 215: Ata_Xfr_Num
CF CONTROLLER S3C6400X RISC MICROPROCESSOR ATA_XFR_NUM Register Address Description Reset Value ATA_XFR_NUM 0x70301934 ATA transfer number 0x0000_0000 ATA_XFR_NUM Bits Description Reset Value XFR_NUM [31:1] Data transfer number. 0x0000_ 0000 Reserved Reserved bits ATA_XFR_CNT Register Address Description Reset Value ATA_XFR_CNT 0x70301938...
Page 216: Ata_Tbuf_Size
S3C6400X RISC MICROPROCESSOR CF CONTROLLER ATA_TBUF_SIZE Register Address Description Reset Value ATA_TBUF_SIZE 0x70301940 ATA size of track buffer 0x0000_0000 ATA_TBUF_SIZE Bits Description Reset Value TRACK_BUFFER_SIZE [31: Size of track buffer (32byte unit). 0x0000000 This must be set to “size_of_data_in_bytes – 1”. For example, to transfer 1-sector (512-byte, 32’h200),...
Page 217 CF CONTROLLER S3C6400X RISC MICROPROCESSOR ATA_CADDR_TBUR Register Address Description Reset Value ATA_CADDR_TBUF 0x7030194C ATA current write address of track buffer 0x0000_0000 ATA_CADDR_TBUF Bits Description Reset Value TRACK_BUF_CUR_ADR [31:2] Current address of track buffer 0x00000000 Reserved [1:0] Reserved bits ATA_CADDR_SBUF Register...
Page 218 S3C6400X RISC MICROPROCESSOR CF CONTROLLER ATA_PIO_FED Register Address Description Reset Value ATA_PIO_FED 0x70301958 ATA PIO device Feature/Error register 0x0000_0000 ATA_PIO_FED Bits Description Reset Value Reserved [31:8] Reserved bits PIO_DEV_FED [7:0] 8-bit PIO device feature/error (command block) 0x00 register * Note: PIO_DEV_FED can be read by accessing register ATA_PIO_RDATA...
Page 219 CF CONTROLLER S3C6400X RISC MICROPROCESSOR ATA_PIO_LMR Address = 0x70301964 Register Address Description Reset Value ATA_PIO_LMR 0x70301964 ATA PIO device LBA middle register 0x0000_0000 ATA_PIO_LMR Bits Description Reset Value Reserved [31:8] Reserved bits PIO_DEV_LMR [7:0] 8-bit PIO device LBA middle (command block)
Page 220 S3C6400X RISC MICROPROCESSOR CF CONTROLLER ATA_PIO_CSD Register Address Description Reset Value ATA_PIO_CSD 0x70301970 ATA PIO device command/status register 0x0000_0000 ATA_PIO_CSD Bits Description Reset Value Reserved [31:8] Reserved bits PIO_DEV_CSD [7:0] 8-bit PIO device command/status (command 0x00 block) register * Note: PIO_DEV_CSD can be read by accessing register ATA_PIO_RDATA.
Page 221 CF CONTROLLER S3C6400X RISC MICROPROCESSOR BUS_FIFO_STATUS Register Address Description Reset Value BUS_FIFO_STATUS 0x70301990 ATA internal AHB FIFO status 0x0000_0000 BUS_FIFO_STATUS Bits Description Reset Value Reserved [31:19] Reserved bits BUS_STATE[2:0] [18:16] 3’b000 : IDLE 0x00 Another value is in operation. Reserved...
Page 222 S3C6400 RISC MICROPROCESSOR GPIO GPIO OVERVIEW S3C6400 includes 188 multi-functional input/output port pins. There are 17 ports as listed below: • GPA : 8 in/out port – UART • GPB : 7 in/out port – UART, IrDA, I2C • GPC : 8 in/out port – SPI •...
Page 223 GPIO S3C6400 RISC MICROPROCESSOR DESCRIPTION GPIO consists of two part, alive-part and off-part. In Alive-part power is supplied on sleep mode, but in off-part it is not the same. Therefore, the registers in alive-part can keep their values during sleep mode. Register File Mux control Pad control...
Page 224 S3C6400 RISC MICROPROCESSOR GPIO REGISTER DESCRIPTION MEMORY MAP Register Address Description Reset Value GPACON 0x7F008000 Port A Configuration Register GPADAT 0x7F008004 Port A Data Register Undefined GPAPUD 0x7F008008 Port A Pull-up/down Register 0x00005555 GPACONSLP 0x7F00800C Port A Sleep mode Configuration Register GPAPUDSLP 0x7F008010 Port A Sleep mode Pull-up/down Register...
Page 225 GPIO S3C6400 RISC MICROPROCESSOR Register Address Description Reset Value GPGCON 0x7F0080C0 Port G Configuration Register GPGDAT 0x7F0080C4 Port G Data Register Undefined GPGPUD 0x7F0080C8 Port G Pull-up/down Register 0x00001555 GPGCONSLP 0x7F0080CC Port G Sleep mode Configuration Register GPGPUDSLP 0x7F0080D0 Port G Sleep mode Pull-up/down Register GPHCON0 0x7F0080E0 Port H Configuration Register...
Page 226 S3C6400 RISC MICROPROCESSOR GPIO Register Address Description Reset Value GPOCON 0x7F008140 Port O Configuration Register 0xAAAAAAAA GPODAT 0x7F008144 Port O Data Register Undefined GPOPUD 0x7F008148 Port O Pull-up/down Register GPOCONSLP 0x7F00814C Port O Sleep mode Configuration Register GPOPUDSLP 0x7F008150 Port O Sleep mode Pull-up/down Register GPPCON 0x7F008160 Port P Configuration Register...
Page 227 GPIO S3C6400 RISC MICROPROCESSOR Register Address Description Reset Value EINT12CON 0x7F008200 External Interrupt 1,2 Configuration Register EINT34CON 0x7F008204 External Interrupt 3,4 Configuration Register EINT56CON 0x7F008208 External Interrupt 5,6 Configuration Register EINT78CON 0x7F00820C External Interrupt 7,8 Configuration Register EINT9CON 0x7F008210 External Interrupt 9 Configuration Register EINT12FLTCON 0x7F008220 External Interrupt 1,2 Filter Control Register...
Page 228 S3C6400 RISC MICROPROCESSOR GPIO INDIVIDUAL REGISTER DESCRIPTIONS PORT A CONTROL REGISTER There are five control registers including GPACON, GPADAT, GPAPUD, GPACONSLP and GPAPUDSLP in the Port A Control Registers. Register Address Description Reset Value GPACON 0x7F008000 Port A Configuration Register 0x0000 GPADAT 0x7F008004...
Page 229 GPIO S3C6400 RISC MICROPROCESSOR GPA7 [31:28] 0000 = Input 0001 = Output 0000 0010 = UART RTSn[1] 0011 = Reserved 0100 = Reserved 0101 = ADDR_CF[1] 0110 = Reserved 0111 = External Interrupt Group 1 [7] GPADAT Description GPA[7:0] [7:0] When the port is configured as input port, the corresponding bit is the pin state.
Page 230 S3C6400 RISC MICROPROCESSOR GPIO PORT B CONTROL REGISTER There are five control registers including GPBCON, GPBDAT, GPBPUD, GPBCONSLP and GPBPUDSLP in the Port B Control Registers. Register Address Description Reset Value GPBCON 0x7F008020 Port B Configuration Register 0x40000 GPBDAT 0x7F008024 Port B Data Register Undefined GPBPUD...
Page 231 GPIO S3C6400 RISC MICROPROCESSOR GPBDAT Description GPB[6:0] [6:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 232 S3C6400 RISC MICROPROCESSOR GPIO PORT C CONTROL REGISTER There are five control registers including GPCCON, GPCDAT, GPCPUD, GPCCONSLP and GPCPUDSLP in the Port C Control Registers. Register Address Description Reset Value GPCCON 0x7F008040 Port C Configuration Register 0x00 GPCDAT 0x7F008044 Port C Data Register Undefined GPCPUD...
Page 233 GPIO S3C6400 RISC MICROPROCESSOR GPCDAT Description GPC[7:0] [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 234 S3C6400 RISC MICROPROCESSOR GPIO PORT D CONTROL REGISTER There are five control registers including GPDCON, GPDDAT, GPDPUD, GPDCONSLP and GPDPUDSLP in the Port D Control Registers. Register Address Description Reset Value GPDCON 0x7F008060 Port D Configuration Register 0x00 GPDDAT 0x7F008064 Port D Data Register Undefined GPDPUD...
Page 235 GPIO S3C6400 RISC MICROPROCESSOR GPDDAT Description GPD[4:0] [4:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 236 S3C6400 RISC MICROPROCESSOR GPIO PORT E CONTROL REGISTERS There are five control registers including GPECON, GPEDAT, GPEPUD GPECONSLP and GPEPUDSLP in the Port E Control Registers. Register Address Description Reset Value GPECON 0x7F008080 Port E Configuration Register 0x00 GPEDAT 0x7F008084 Port E Data Register Undefined GPEPUD...
Page 237 GPIO S3C6400 RISC MICROPROCESSOR GPEDAT Description GPE[15:0] [4:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 238 S3C6400 RISC MICROPROCESSOR GPIO PORT F CONTROL REGISTERS There are five control registers including GPFCON, GPFDAT, GPFPUD, GPFECONSLP and GPFPUDSLP in the Port F Control Registers. Register Address Description Reset Value GPFCON 0x7F0080A0 Port F Configuration Register 0x00 GPFDAT 0x7F0080A4 Port F Data Register Undefined GPFPUD...
Page 239 GPIO S3C6400 RISC MICROPROCESSOR GPF14 [29:28] 00 = Input 01 = Output 10 = PWM TOUT[0] 11 = CLKOUT[0] GPF15 [31:30] 00 = Input 01 = Output 10 = PWM TOU[1] 11 = Reserved GPFDAT Description GPF[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 240 S3C6400 RISC MICROPROCESSOR GPIO PORT G CONTROL REGISTERS There are five control registers including GPGCON, GPGDAT, GPGPU, GPGECONSLP and GPGPUDSLP in the Port G Control Registers. Note that 400FBGA package does not support port G. Register Address Description Reset Value GPGCON 0x7F0080C0 Port G Configuration Register...
Page 241 GPIO S3C6400 RISC MICROPROCESSOR GPGDAT Description GPG[6:0] [6:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 242 S3C6400 RISC MICROPROCESSOR GPIO PORT H CONTROL REGISTERS There are six control registers including GPHCON0, GPHCON1, GPHDAT, GPHPUD, GPHCONSLP and GPHPUDSLP in the Port H Control Registers. Register Address Description Reset Value GPHCON0 0x7F0080E0 Port H Configuration Register 0x00 GPHCON1 0x7F0080E4 Port H Configuration Register 0x00...
Page 243 GPIO S3C6400 RISC MICROPROCESSOR GPHCON1 Description Initial State GPH8 [3:0] 0000 = Input 0001 = Output 0000 0010 = MMC DATA1[6] 0011 = MMC DATA2[2] 0100 = Reserved 0101 = Reserved 0110 = ADDR_CF[2] 0111 = External Interrupt Group 6[8] GPH9 [7:4] 0000 = Input...
Page 244 S3C6400 RISC MICROPROCESSOR GPIO PORT I CONTROL REGISTERS There are five control registers including GPICON, GPIDAT, GPIPUD, GPICONSLP ,and GPIPUDSLP in the Port I Control Registers. Register Address Description Reset Value GPICON 0x7F008100 Port I Configuration Register 0x00 GPIDAT 0x7F008104 Port I Data Register Undefined GPIPUD...
Page 245 GPIO S3C6400 RISC MICROPROCESSOR GPI14 [29:28] 00 = Input 01 = Output 10 = LCD VD[14] 11 = reserved GPI15 [31:30] 00 = Input 01 = Output 10 = LCD VD[15] 11 = reserved GPIDAT Description GPI[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 246 S3C6400 RISC MICROPROCESSOR GPIO PORT J CONTROL REGISTERS There are five control registers including GPJCON, GPJDAT, and GPJPUD, GPJCONSLP and GPJPUDSLP in the Port J Control Registers. Register Address Description Reset Value GPJCON 0x7F008120 Port J Configuration Register 0x00 GPJDAT 0x7F008124 Port J Data Register Undefined...
Page 247 GPIO S3C6400 RISC MICROPROCESSOR GPJDAT Description GPJ[15:0] [11:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 248 S3C6400 RISC MICROPROCESSOR GPIO PORT K CONTROL REGISTERS There are four control registers including GPKCON0, GPKCON1, GPKDAT, and GPKPUD in the Port K Control Registers. Register Address Description Reset Value GPKCON0 0x7F008800 Port K Configuration Register 0 0x22222222 GPKCON1 0x7F008804 Port K Configuration Register 1 0x22222222 GPKDAT...
Page 249 GPIO S3C6400 RISC MICROPROCESSOR GPKCON1 Description Initial State GPK8 [3:0] 0000 = Input 0001 = Output 0010 0010 = Host I/F DATA[8] 0011 = Key pad ROW[0] 0100 = Reserved 0101 = DATA_CF[8] 0110 = Reserved 0111 = Reserved GPK9 [7:4] 0000 = Input 0001 = Output...
Page 250 S3C6400 RISC MICROPROCESSOR GPIO GPKDAT Description GPK[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 251 GPIO S3C6400 RISC MICROPROCESSOR PORT L CONTROL REGISTERS There are four control registers including GPLCON0, GPLCON1, GPLDAT and GPLPUD, in the Port L Control Registers. Register Address Description Reset Value GPLCON0 0x7F008810 Port L Configuration Register 0 0x22222222 GPLCON1 0x7F008814 Port L Configuration Register 1 0x02222222 GPLDAT...
Page 252 S3C6400 RISC MICROPROCESSOR GPIO GPLCON1 Description Initial State GPL8 [3:0] 0000 = Input 0001 = Output 0010 0010 = Host I/F ADDR[8] 0011 = Ext. Interrupt[16] 0100 = Reserved 0101 = CE_CF[0] 0110 = Reserved 0111 = OTG ULPI STP GPL9 [7:4] 0000 = Input...
Page 253 GPIO S3C6400 RISC MICROPROCESSOR GPLDAT Description GPL[14:0] [14:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 254 S3C6400 RISC MICROPROCESSOR GPIO PORT M CONTROL REGISTERS There are three control registers including GPMCON, GPMDAT and GPMPUD in the Port M Control Registers. Register Address Description Reset Value GPMCON 0x7F008820 Port M Configuration Register 0x00222222 GPMDAT 0x7F008824 Port M Data Register Undefined GPMPUD 0x7F008828...
Page 255 GPIO S3C6400 RISC MICROPROCESSOR GPLPUD Description GPM[n] [2n+1:2n] 00 = pull-up/down disabled n = 0~5 01 = pull-down enabled 10 = pull-up enabled 11 = Reserved. Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 256 S3C6400 RISC MICROPROCESSOR GPIO PORT N CONTROL REGISTERS There are three control registers including GPNCON, GPNDAT and GPNPUD in the Port N Control Registers. Register Address Description Reset Value GPNCON 0x7F008830 Port N Configuration Register 0x00 GPNDAT 0x7F008834 Port N Data Register Undefined GPNPUD 0x7F008838...
Page 257 GPIO S3C6400 RISC MICROPROCESSOR GPNDAT Description GPN[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 258 S3C6400 RISC MICROPROCESSOR GPIO PORT O CONTROL REGISTERS There are five control registers including GPOCON, GPODAT, GPOPUD, POCONSLP and GPOPUDSLP in the Port O Control Registers. Register Address Description Reset Value GPOCON 0x7F008140 Port O Configuration Register 0xAAAAAAAA GPODAT 0x7F008144 Port O Data Register Undefined GPOPUD...
Page 259 GPIO S3C6400 RISC MICROPROCESSOR GPO14 [29:28] 00 = Input 01 = Output 10 = MEM0_ADDR[14] 11 = Ext. Interrupt Group7 [14] GPO15 [31:30] 00 = Input 01 = Output 10 = MEM0_ADDR[15] 11 = Ext. Interrupt Group7 [15] GPODAT Description GPO[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state.
Page 260 S3C6400 RISC MICROPROCESSOR GPIO PORT P CONTROL REGISTERS There are five control registers including GPPCON, GPPDAT, GPPPUD, GPPCONSLP and GPPPUDSLP in the Port P Control Registers. Register Address Description Reset Value GPPCON 0x7F008160 Port P Configuration Register 0x2AAAAAAA GPPDAT 0x7F008164 Port P Data Register Undefined GPPPUD...
Page 261 GPIO S3C6400 RISC MICROPROCESSOR GPP14 [29:28] 00 = Input 01 = Output 10 = MEM0_CData 11 = Ext. Interrupt Group8 [14] GPPDAT Description GPP[14:0] [14:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 262 S3C6400 RISC MICROPROCESSOR GPIO PORT Q CONTROL REGISTERS There are five control registers including GPQCON, GPQDAT, GPQPUD, GPQCONSLP and GPQPUDSLP in the Port Q Control Registers. Register Address Description Reset Value GPQCON 0x7F008180 Port Q Configuration Register 0x0002AAAA GPQDAT 0x7F008184 Port Q Data Register Undefined GPQPUD...
Page 263 GPIO S3C6400 RISC MICROPROCESSOR GPQPUD Description GPQ[n] [2n+1:2n] 00 = pull-up/down disabled n = 0~8 01 = pull-down enabled 10 = pull-up enabled 11 = Reserved. GPQCONSLP Description Initial State GPQ[n] [2n+1:2n] 00 = output 0 n = 0~8 01 = output 1 10 = input 11 = Previuos state GPQPUDSLP...
Page 264 S3C6400 RISC MICROPROCESSOR GPIO SPECIAL PORT CONTROL REGISTER Register Address Description Reset Value SPCON 0x7F0081A0 Special Port Control Register 0x00011500 SPCON Description Initial State Reserved [31:21] Reserved 0x000 nRSTOUT_OEN [20] Reset Out pin(XnRSTOUT) output enable 0 = enable 1 = disable (hi-Z) Reserved [19:18] Reserved...
Page 265 GPIO S3C6400 RISC MICROPROCESSOR LCD_SEL[1:0] XvVD[6:0] XvSYS_VD[6:0] XvRGBVD[6:0] XvVD[13:7] XvSYS_VD[13:7] XvRGBVD[13:7] XvVD[15:14] XvSYS_VD[15:14] XvRGBVD[15:14] XvVD[17:16] XvSYS_VD[17:16] XvRGBVD[17:16] XvVD[20:18] XvRGBVD[20:18] XvVD[21] XvRGBVD[21] Reserved Reserved XvVD[22] XvSYS_VSYNC_ldi XvRGBVD[22] XvVD[23] XvSYS_OEn XvRGBVD[23] XvHSYNC XvSYS_CSn_main XvHSYNC XvVSYNC XvSYS_CSn_sub XvVSYNC XvVDEN XvSYS_RS XvVDEN XvVCLK XvSYS_WEn XvVCLK USB 1.0 Tranceiver 0.5K...
Page 266 S3C6400 RISC MICROPROCESSOR GPIO GPIO Off-part CPU I/F GPICON GPJCON Bypass Controller Port (I, J port) LCD_SEL[1:0] (SPCON[1:0]) Modem I/F Port Off-part (K,L,M Other port) function blocks GPKCON GPLCON GPMCON GPIO alive-part GPICONSLP GPJCONSLP Bypass SEL_BYPASS (MIFPCON[3]) Modem I/F Alive-part Port Mux Alive (K,L,M...
Page 267 GPIO S3C6400 RISC MICROPROCESSOR MEMORY INTERFACE PIN CONFIGURATION REGISTER IN STOP MODE Register Address Description Reset Value MEM0CONSTOP 0x7F0081B0 Memory Port 0 Configuration Register MEM1CONSTOP 0x7F0081B4 Memory Port 1 Configuration Register MEM0CONSTOP Description Initial State Reserved [31:29] Reserved MEM0_RESET [28] Memory port 0 RESET pin (Xm0RESET) Configure 0 = Previous state 1 = Hi-Z...
Page 268 S3C6400 RISC MICROPROCESSOR GPIO MEM0_CSn [12] Memory port 0 Chip Select pin (Xm0CSn) Configure 0 = Previous state 1 = Hi-Z Reserved [11:7] Reserved MEM0_nWEdmc Memory port 0 Dram Write Enable pin (Xm0nWEdmc) Configure 0 = Previous state 1 = Hi-Z MEM0_AP Memory port 0 AP pin (Xm0AP) Configure 0 = Previous state...
Page 269 GPIO S3C6400 RISC MICROPROCESSOR MEM1CONSTOP Description Initial State Reserved [31:21] reserved 0x0000 MEM1_SCLKn [20] Memory port 1 SCLKn pin (Xm1SCLKn) Configure 0 = Previous state 1 = Hi-Z MEM1_SCLK [19] Memory port 1 SCLK pin (Xm1SCLK) Configure 0 = Previous state 1 = Hi-Z MEM1_CKE [18]...
Page 270 S3C6400 RISC MICROPROCESSOR GPIO MEMORY INTERFACE PIN CONFIGURATION REGISTER IN SLEEP MODE Register Address Description Reset Value MEM0CONSLP0 Memory Port 0 pin Configuration Register 0 0x7F0081C0 MEM0CONSLP1 Memory Port 0 pin Configuration Register 1 0x7F0081C4 MEM1CONSLP 0x7F0081C8 Memory Port 1 pin Configuration Register MEM0CONSLP0 Description Initial State...
Page 271 GPIO S3C6400 RISC MICROPROCESSOR MEM0_nWEdmc [7:6] Memory port 0 Dram Write Enable pin (Xm0nWEdmc) Configure 00 = output 0, 01 = output 1 1x = output disable ( hi-Z ) MEM0_AP [5:4] Memory port 0 AP pin (Xm0AP) Configure 00 = output 0, 01 = output 1 1x = output disable ( hi-Z ) MEM0_D...
Page 272 S3C6400 RISC MICROPROCESSOR GPIO MEM0_INTsm0_F [7:6] Memor port 0 FWEn pin(Xm0INTsm0_FWEn) Configure 00 = output 0, 01 = output 1 1x = output disable ( hi-Z ) MEM0_RDY0_CLE [5:4] Memor port 0 CLE pin(Xm0RDY0_CLE) Configure 00 = output 0, 01 = output 1 1x = output disable ( hi-Z ) MEM0_RDY1_ALE [3:2]...
Page 273 GPIO S3C6400 RISC MICROPROCESSOR 0000 = output 0 0001 = output 1 0100 = input ( hi-Z ) 0101 = input pull-down enable 0110 = inupt pull-up enable 0111 = do not use 10xx = Previous state MEM1_D1 [7:4] Memory Port 1 Data pin[31:16](Xm1DATA[31:16]) Configure 0000 = output 0 0001 = output 1 0100 = input ( hi-Z )
Page 274 S3C6400 RISC MICROPROCESSOR GPIO MEMORY INTERFACE DRIVE STRENGTH CONTROL REGISTER Register Address Description Reset Value MEM0DRVCON 0x7F0081D0 Memory Port 0 Drive strength Control Register MEM1DRVCON 0x7F0081D4 Memory Port 1 Drive strength Control Register MEM0DRVCON Description Initial State Reserved [31:30] Reserved MEM0_ADDRVLD_ [29:28] Memory port 0 ADDRVLD, RP pin (Xm0ADDRVLD, Xm0RP)
Page 275 GPIO S3C6400 RISC MICROPROCESSOR MEM1DRVCON Description Initial State Reserved [31:24] reserved 0x00 MEM1_SCLKn [23:22] Memory port 1 SCLKn pin (Xm1SCLKn) Configure MEM1_DQS [21:20] Memory port 1 DQS pin (Xm1DQS) Configure MEM1_CKE [19:18] Memory port 1 CKE pin (Xm1CKE) Configure MEM1_SCLK [17:16] Memory port 1 SCLK pin (Xm1SCLK) Configure MEM1_A...
Page 276 S3C6400 RISC MICROPROCESSOR GPIO EXTERNAL INTERRUPT CONTROL REGISTERS External Interrupt is consists of 10 groups numbered from 0 to 9. Only external interrupt group 0 is used for wake- up source in Stop and Sleep mode. And, In idle mode, all interrupts can be wake-up source, the other groups of external interrupts also can be the sources.
Page 277 GPIO S3C6400 RISC MICROPROCESSOR EINT9PEND 0x7F008270 External Interrupt 9 Pending Register PRIORITY 0x7F008280 Priority Control Register 0x3FF SERVICE 0x7F008284 Current Service Register 0x00 SERVICEPEND 0x7F008288 Current Service Pending Register 0x00 Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 278 S3C6400 RISC MICROPROCESSOR GPIO EINT0CON0 Description Initial State Reserved [31] Reserved EINT15, 14 [30:28] Setting the signaling method of the EINT15 and EINT14. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved [27]...
Page 279 GPIO S3C6400 RISC MICROPROCESSOR EINT0CON1 Description Initial State Reserved [31:23] Reserved 000000000 EINT27, 26 [22:20] Setting the signaling method of the EINT27 and EINT26. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved [19]...
Page 280 S3C6400 RISC MICROPROCESSOR GPIO FLTSEL [22] Filter Selection for EINT4, 5 0 = delay filter 1 = digital filter(clock count) EINT4, 5 [21:16] Filtering width of EINT4, 5 This value is valid when FLTSEL is 1. FLTEN [15] Filter Enable for EINT2, 3 0 = disables 1 = enabled FLTSEL...
Page 281 GPIO S3C6400 RISC MICROPROCESSOR EINT0FLTCON2 Description Initial State FLTEN [31] Filter Enable for EINT 22, 23 0 = disables 1 = enabled FLTSEL [30] Filter Selection for EINT 22, 23 0 = delay filter 1 = digital filter(clock count) EINT22, 23 [29:24] Filtering width of EINT22, 23 This value is valid when FLTSEL is 1.
Page 282 S3C6400 RISC MICROPROCESSOR GPIO EINT0MASK Description Initial State EINT27 [27] 0 = Enable Interrupt 1= Masked EINT26 [26] 0 = Enable Interrupt 1= Masked EINT25 [25] 0 = Enable Interrupt 1= Masked EINT24 [24] 0 = Enable Interrupt 1= Masked EINT23 [23] 0 = Enable Interrupt...
Page 283 GPIO S3C6400 RISC MICROPROCESSOR EINT0PEND Description Initial State EINT27 [27] 0 = Not occur 1= Occur interrupt EINT26 [26] 0 = Not occur 1= Occur interrupt EINT25 [25] 0 = Not occur 1= Occur interrupt EINT24 [24] 0 = Not occur 1= Occur interrupt EINT23 [23]...
Page 284 S3C6400 RISC MICROPROCESSOR GPIO EINT12CON Description Initial State Reserved [31:23] Reserved EINT2[7:4] [22:20] Setting the signaling method of the EINT2[7:4]. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved [19] Reserved...
Page 285 GPIO S3C6400 RISC MICROPROCESSOR EINT34CON Description Initial State Reserved [31] Reserved EINT4[13:12] [30:28] Setting the signaling method of the EINT4[13:12]. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved [27] Reserved...
Page 286 S3C6400 RISC MICROPROCESSOR GPIO EINT56CON Description Initial State Reserved [31:27] Reserved EINT6[9:8] [26:24] Setting the signaling method of the EINT6[9:8]. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved [23] Reserved...
Page 287 GPIO S3C6400 RISC MICROPROCESSOR EINT78CON Description Initial State Reserved [31] Reserved EINT8[14:12] [30:28] Setting the signaling method of the EINT8[14:12]. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved [27] Reserved...
Page 288 S3C6400 RISC MICROPROCESSOR GPIO EINT9CON Description Initial State Reserved [31:7] Reserved 0x000000 EINT9[8:4] [6:4] Setting the signaling method of the EINT9[8:4]. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved Reserved EINT9[3:0]...
Page 289 GPIO S3C6400 RISC MICROPROCESSOR EINT12FLTCON Description Initial State Reserved [31:24] Rreserved 0x00 FLTEN2[7:0] [23] Filter Enable for EINT2[7:0] 0 = disables 1 = enabled EINT2[7:0] [22:16] Filtering width of EINT2[7:0] FLTEN1[14:8] [15] Filter Enable for EINT1[14:8] 0 = disables 1 = enabled EINT1[14:8] [14:8] Filtering width of EINT1[14:8]...
Page 290 S3C6400 RISC MICROPROCESSOR GPIO EINT56FLTCON Description Initial State FLTEN6[9:8] [31] Filter Enable for EINT6[9:8] 0 = disables 1 = enabled EINT6[9:8] [30:24] Filtering width of EINT6[9:8] FLTEN6[7:0] [23] Filter Enable for EINT6[7:0] 0 = disables 1 = enabled EINT6[7:0] [22:16] Filtering width of EINT6[7:0] Reserved [15:8]...
Page 291 GPIO S3C6400 RISC MICROPROCESSOR EINT12MASK Description Initial State Reserved [31:24] Reserved [16+m] EINT2[m] 0 = Enable Interrupt 1= Masked m = 0 ~ 7 Reserved [15] Reserved EINT1[n] 0 = Enable Interrupt 1= Masked n = 0 ~ 14 EINT34MASK Description Initial State Reserved...
Page 292 S3C6400 RISC MICROPROCESSOR GPIO EINT12PEND Description Initial State Reserved [31:24] Reserved [16+m] EINT2[m] 0 = Not occur 1= Occur interrupt m = 0 ~ 7 Reserved [15] Reserved EINT1[n] 0 = Not occur 1= Occur interrupt n = 0 ~ 14 EINT34PEND Description Initial State...
Page 293 GPIO S3C6400 RISC MICROPROCESSOR PRIORITY REGISTER (PRIORITY) Register Address Description Reset Value PRIORITY 0x7F008280 External Interrupt priority control register 0x000003FF PRIORITY Description Initial State ARB9 External Interrupt Group 9 priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable ARB8 External Interrupt Group 8 priority rotate enable 0 = Priority does not rotate,...
Page 294 S3C6400 RISC MICROPROCESSOR GPIO ARBITER1 EINT1[14:0] ARBITER2 EINT2[7:0] Interrupt ARBITER0 ARBITER3 EINT3[4:0] ARBITER4 EINT4[13:0] ARBITER5 EINT5[6:0] ARBITER6 EINT6[9:0] ARBITER7 EINT7[15:0] ARBITER8 EINT8[14:0] ARBITER9 EINT9[8:0] Figure 10-４ Priority Generating Block Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 295 GPIO S3C6400 RISC MICROPROCESSOR CURRENT SERVICE REGISTER (SERVICE) Current Service Register presents which interrupt should be serviced. The bit values describe the group number and interrupt number. This value is decided by the PRIORITY register and valid when nIRQ is generated. Current Service Pending Register presents which interrupt pending bit must be cleared.
Page 296 S3C6400 RISC MICROPROCESSOR GPIO EXTERN PIN CONFIGURATION REGISTER IN SLEEP MODE These registers keep their values during sleep mode. Register Address Description Reset Value SPCONSLP 0x7F008880 Special Port Sleep mode configure Register 0x0000010 SLPEN 0x7F008930 Sleep mode Pad Configuer Register. 0x00 SPCONSLP Description...
Page 297: Dma Controller
S3C6400 RISC MICROPROCESSOR DMA CONTROLLER This chapter describes the DMA controller for the S3C6400 RSIC microprocessor. OVERVIEW S3C6400 contains four DMA controllers. Each DMA controller consists of 8 transfer channels. Each channel of DMA controller can perform data movements between devices in the SPINE AXI bus and/or PERIPHERAL AXI bus through AHBtoAXI bridges without any restrictions.
Page 298 S3C6400 RISC MICROPROCESSOR peripheral transfers. Scatter or gather DMA is supported through the use of linked lists. Hardware DMA channels priority. Each DMA channel has a specific hardware priority. DMA channel 0 has the highest priority down to channel 7 which has the lowest priority. If requests from two channels become active at the same time the channel with the highest priority is serviced first.
Page 299 S3C6400 RISC MICROPROCESSOR BLOCK DIAGRAM Figure 11-1. DMAC block diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 11-3 Specifications and information herein are subject to change without notice.
Page 300 S3C6400 RISC MICROPROCESSOR DMA SOURCES The S3C6400 supports 64 DMA sources as listed in the table below. Group DMA No. Sources Description DMA0, SDMA0 DMA_UART0[0] UART0 DMA source 0 DMA0, SDMA0 DMA_UART0[1] UART0 DMA source 1 DMA0, SDMA0 DMA_UART1[0] UART1 DMA source 0 DMA0, SDMA0 DMA_UART1[1] UART1 DMA source 1...
Page 301 S3C6400 RISC MICROPROCESSOR DMA1, SDMA1 DMA_PWM PWM DMA source DMA1, SDMA1 DMA_IrDA IrDA DMA source DMA1, SDMA1 DMA_EXTERNAL External DMA source DMA1, SDMA1 Reserved DMA1, SDMA1 Reserved SDMA1 DMA_SECU_RX Security RX DMA source SDMA1 DMA_SECU_TX Security TX DMA source Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 302 S3C6400 RISC MICROPROCESSOR DMA INTERFACE DMA request signals The DMA request signals are used by peripherals to request a data transfer. The DMA request signals indicate: Whether a single word or a burst (multi-word)transfer of data is required Whether the transfer is the last in the data packet. The DMA request signals to the DMA controller for each peripheral are as follows: DMACxBREQ : Burst request signal.
Page 303 S3C6400 RISC MICROPROCESSOR Peripheral-to-memory transaction under DMA controller flow control For transactions that are not a multiple of the burst size, use both the burst and single request signals as shown in Figure 11-2. DMACBREQ DMACSREQ Peripheral controller DMACCLR Figure 11-2. Peripheral-to-memory transaction comprising bursts and single requests The two request signals are not mutually exclusive.
Page 304 S3C6400 RISC MICROPROCESSOR Memory controller AMBA bus Figure 11-4. Memory-to-memory transaction under DMA flow control Peripheral-to-peripheral transaction under DMA controller flow control When the transaction is not a multiple of the burst size, use the following signals: The single and burst request signals (DMACBREQ and DMACSREQ )of the source peripheral The burst request signal (DMACBREQ ) of the destination peripheral.
Page 305 S3C6400 RISC MICROPROCESSOR Signal timing The timing behavior of the DMA signals is described below: DMA request signal DMAC{L}(B/S)REQx Notifies the DMA controller about the peripheral which is ready to proceed with a DMA transfer of the indicated size. Active HIGH. Sampled by the DMA controller on the positive edge of HCLK .The DMA request signals are used in conjunction with the DMACCLR signal to perform handshaking.
Page 306 S3C6400 RISC MICROPROCESSOR FUNCTIONAL TIMING DIAGRAM A peripheral asserts a DMA request and holds it active. The DMACCLR signal is asserted by the DMA controller when the last data item has been transferred. When the peripheral notice that the DMACCLR signal has gone active it makes the DMA request signal inactive.
Page 307 S3C6400 RISC MICROPROCESSOR Disabling a DMA channel A DMA channel can be disabled in following three ways: Write directly to the Channel Enable bit. Any outstanding data in the FIFOs will be lost if this method is used. Use the Active and Halt bits in conjunction with the Channel Enable bit. Wait until the transfer completes.
Page 308 S3C6400 RISC MICROPROCESSOR Offset Contents Next LLI address Source Address for next transfer Next LLI address + 0x04 Destination Address for next transfer Next LLI address + 0x08 Next LLI address for next transfer Next LLI address + 0x0C DMACCxControl0 data for next transfer Next LLI address + 0x10 DMACCxControl1 data for next transfer 7.
Page 309 S3C6400 RISC MICROPROCESSOR REGISTER DESCRIPTION There are four DMA Controller named as DMAC0, DMAC1, SDMAC0, and SDMAC1. The register base addresses of DMAC0, DMAC1, SDMAC0, and SDMAC1 are 0x7500_0000, 0x7510_0000, 0x7DB0_0000, and 0x7DC0_0000 respectively. Page- access feature for OneNAND Controller is added to channel 3 of DMAC0 and SDAMC0. DMA register location Table 11-1 DMA register summary Name...
Page 310 S3C6400 RISC MICROPROCESSOR Table 11-1 DMA register summary (continued) Name Type Width Description Offset Reset Value DMACSoftBReq This register allows DMA burst requests to be 0x020 0x0000 generated by software. DMACSoftSReq This register allows DMA single requests to be 0x024 0x0000 generated by software.
Page 311 S3C6400 RISC MICROPROCESSOR Table 11-1 DMA register summary (continued) Name Type Width Description Offset Reset Value DMACC4SrcAddr DMA channel 4 source address. 0x180 0x00000000 DMACC4DestAddr DMA channel 4 destination address. 0x184 0x00000000 DMACC4LLI DMA channel 4 linked list address. 0x188 0x00000000 DMACC4Control0 DMA channel 4 control0.
Page 312 S3C6400 RISC MICROPROCESSOR Interrupt status register, DMACIntStatus The DMACIntStatus register is read-only and indicates the status of the interrupts after masking. A HIGH bit indicates that a specific DMA channel interrupt request is active. The request can be generated from either the error or terminal count interrupt requests.
Page 313 S3C6400 RISC MICROPROCESSOR Interrupt error status register, DMACIntErrorStatus The DMACIntErrorStatus register is read-only register and indicates the status of the error request after masking. This register must be used in conjunction with the DMACIntStatus register if the combined interrupt request, DMACINTCOMBINE, is used to request interrupts.
Page 314 S3C6400 RISC MICROPROCESSOR Raw error interrupt status register, DMACRawIntErrorStatus The DMACRawIntErrorStatus register is read-only. It indicates which DMA channels are requesting an error interrupt prior to masking. A HIGH bit indicates that the error interrupt request is active prior to masking. Table 11-8 shows the bit assignment of register of the DMACRawIntErrorStatus register.
Page 315 S3C6400 RISC MICROPROCESSOR Software single request register, DMACSoftSReq The DMACSoftSReq read/write register allows DMA single requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction is complete.
Page 316 S3C6400 RISC MICROPROCESSOR Configuration register, DMACConfiguration The DMACConfiguration read/write register is used to configure the operation of the DMA controller. The endianness of the individual AHB master interfaces can be altered by writing to the M1 and M2 bits of this register. The M1 bit allows the endianness of AHB master interface 1 to be altered.
Page 317 S3C6400 RISC MICROPROCESSOR synchronization logic improves the DMA request response time. If necessary, the DMA response signals, DMACCLR and DMACTC, must be synchronized in the peripheral. Channel source address register, DMACCxSrcAddr The eight read/write DMACCxSrcAddr registers contain the current source address (byte-aligned) of the data to be transferred.
Page 318 S3C6400 RISC MICROPROCESSOR Channel linked list item register, DMACCxLLI The eight read/write DMACCxLLI registers contain a word aligned address of the next Linked List Item (LLI). If the LLI is, then the current LLI is the last in the chain, and the DMA channel is disabled once all DMA transfers associated with it are completed.
Page 319 S3C6400 RISC MICROPROCESSOR Table 11-19. Bit Assignment of DMACCxControl register (continued) DMACCxControl Bits Type Function Source AHB master select: [24] 0 = AHB master 1 (AXI_SPINE) selected for the source transfer 1 = AHB master 2 (AXI_PERI) selected for the source transfer. Destination transfer width.
Page 320 S3C6400 RISC MICROPROCESSOR Table 11-22. Protection bits Bits Description Purpose Indicates that the access is in User, or privileged mode: Privileged or 0 = User mode User 1 = privileged mode. This bit controls the AHB HPROT[1] signal. Indicates that the access is bufferable, or not bufferable: Bufferable or 0 = not bufferable not bufferable...
Page 321 S3C6400 RISC MICROPROCESSOR Channel configuration register, DMACCxConfiguration The eight DMACCxConfiguration registers are read/write and are used to configure the DMA channel. The registers are not updated when a new LLI is requested. Table 11-24 shows the bit assignment of a DMACCxConfiguration register. Table 11-24.
Page 322 S3C6400 RISC MICROPROCESSOR Source peripheral. This value selects the DMA source request SrcPeripheral [4:1] peripheral. This field is ignored if the source of the transfer is from memory. Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled 1 = channel enabled.
Page 323 S3C6400X RISC MICROPROCESSOR NOTE 11-27...
Page 324 OVERVIEW The interrupt controller in the S3C6400X is composed of 2 VIC’s (Vectored Interrupt Controller, ARM PrimeCell PL192) and 2 TZIC’s (TrustZone Interrupt Controller, SP890). Two TZIC’s and VIC’s are daisy-chained to support up to 64 interrupt sources. The TZIC provides a software interface to the secure interrupt system in a TrustZone design.
Page 325 INT SOURCE[31:0] TZIC0 VIC0 IRQOUT[31:0] nTZICFIQ Figure 12-1 Interrupt Controller in S3C6400X INTERRUPT SOURCES The S3C6400X supports 64 interrupt sources as shown in the table below. Int. No. Sources Description Group INT_ADC ADC EOC interrupt TZIC1, VIC1 INT_PENDN...
Page 326 S3C6400X RISC MICROPROCESSOR VECTORED INTERRUPT CONTROLLER INT_NFC NFCON interrupt TZIC1, VIC1 INT_ONENAND1 OneNAND interrupt from bank 1 TZIC1, VIC1 INT_ONENAND0 OneNAND interrupt from bank 0 TZIC1, VIC1 INT_DMA1 DMA1 interrupt TZIC1, VIC1 INT_DMA0 DMA0 interrupt TZIC1, VIC1 INT_UART3 UART3 interrupt...
Page 327 VECTORED INTERRUPT CONTROLLER S3C6400X RISC MICROPROCESSOR Reserved TZIC0, VIC0 Reserved TZIC0, VIC0 Reserved TZIC0, VIC0 Reserved TZIC0, VIC0 INT_CAMIF_P Camera interface interrupt TZIC0, VIC0 INT_CAMIF_C Camera interface interrupt TZIC0, VIC0 INT_RTC_TIC RTC TIC interrupt TZIC0, VIC0 INT_EINT1 External interrupt 4 ~ 11...
Page 328 S3C6400X RISC MICROPROCESSOR VECTORED INTERRUPT CONTROLLER FUNCTION BLOCK DIAGRAM Figure 12-2 Vectored Interrupt Controller block diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 12-5 Specifications and information herein are subject to change without notice.
Page 329 VECTORED INTERRUPT CONTROLLER S3C6400X RISC MICROPROCESSOR SUMMARY OF VIC REGISTERS Base address of VIC0 is 0x7120_0000 Base address of VIC1 is 0x7130_0000 Address of control register = base address + offset Register Offset Type Description Reset Value VICIRQSTATUS 0x000 IRQ Status Register...
Page 330 S3C6400X RISC MICROPROCESSOR VECTORED INTERRUPT CONTROLLER VICVECTADDR19 0x14C Vector Address 19 Register 0x00000000 VICVECTADDR20 0x150 Vector Address 20 Register 0x00000000 VICVECTADDR21 0x154 Vector Address 21 Register 0x00000000 VICVECTADDR22 0x158 Vector Address 22 Register 0x00000000 VICVECTADDR23 0x15C Vector Address 23 Register...
Page 331 VECTORED INTERRUPT CONTROLLER S3C6400X RISC MICROPROCESSOR VICVECTPRIORITY24 0x260 Vector Priority 24 Register VICVECTPRIORITY25 0x264 Vector Priority 25 Register VICVECTPRIORITY26 0x268 Vector Priority 26 Register VICVECTPRIORITY27 0x26C Vector Priority 27 Register VICVECTPRIORITY28 0x270 Vector Priority 28 Register VICVECTPRIORITY29 0x274 Vector Priority 29 Register...
Page 332 S3C6400X RISC MICROPROCESSOR VECTORED INTERRUPT CONTROLLER REGISTER DESCRIPTIONS IRQ Status Register, VICIRQSTATUS Bits Name Type Function [31:0] IRQStatus Show the status of the interrupts after masking by the VICINTENABLE and VICINTSELECT Registers: 0 = interrupt is inactive (reset) 1 = interrupt is active.
Page 333 VECTORED INTERRUPT CONTROLLER S3C6400X RISC MICROPROCESSOR 1 = FIQ interrupt There is one bit of the register for each interrupt source. Interrupt Enable Register, VICINTENABLE Bits Name Type Function Enables the interrupt request lines, which allow the [31:0] IntEnable interrupts to reach the processor.
Page 334 S3C6400X RISC MICROPROCESSOR VECTORED INTERRUPT CONTROLLER Read: 0 = software interrupt inactive (reset) 1 = software interrupt active Write: 0 = no effect 1 = software interrupt enabled There is one bit of the register for each interrupt source. Software Interrupt Clear Register, VICSOFTINTCLEAR...
Page 335 VECTORED INTERRUPT CONTROLLER S3C6400X RISC MICROPROCESSOR Vector Address Register, VICADDRESS Bits Name Type Function Contains the address of the currently active ISR, with [31:0] VectAddr reset value 0x00000000. A read of this register returns the address of the ISR and sets the current interrupt as being serviced.
Page 336 S3C6400X RISC MICROPROCESSOR VECTORED INTERRUPT CONTROLLER Peripheral Identification Registers, VICPERIPHID0-3 VICPERIPHID0 Register Bits Name Type Function Reserved, read as zero, do not modify. [31:8] These bits read back as 0x192 [7:0] Partnumber0 VICPERIPHID1 Register Bits Name Type Function Reserved, read as zero, do not modify.
Page 337 VECTORED INTERRUPT CONTROLLER S3C6400X RISC MICROPROCESSOR PrimeCell Identification Registers, VICPCELLID0-3 VICPCELLID0 Register Bits Name Type Function Reserved, read as zero, do not modify. [31:8] These bits read back as 0x0D. [7:0] VICPCellID0 VICPCELLID1 Register Bits Name Type Function Reserved, read as zero, do not modify.
Page 338 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM SECURITY SUB-SYSTEM OVERVIEW Security sub-system (SsS) is a crypto function accelerator targeted for general purpose mobile processors such as the Application Processor (AP) and Modem chip. The architecture of SsS also provides high-speed bulk data processing, by providing double-layer AHB bus and FIFOs.
Page 339 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR Figure 13-1, Block Diagram of the Security Sub-System Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 13-2 Specifications and information herein are subject to change without notice.
Page 340 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM SPECIAL FUNCTION REGISTERS Security Sub-system Register Map Table 1 DMA & Interrupt Control Register Map Address Reset value Name Description Base + 0x00 0x0000_0000 DnI_CFG DMA and interrupt configuration register * Base = 0x7D00_0000 Table 2 FIFO-Rx Register Map...
Page 341 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR Table 4 AES Register Map Address Reset value Name Description Rx-AES Register Map (Rx side) Base + 0x00 0x0000_0200 AES_Rx_CTRL AES Rx Contrl / Status Reg. Base + 0x10 0x0000_0000 AES_Rx_DIN_01 AES Rx Data Input Reg. 01...
Page 342 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM Table 5 DES/TDES Register Map Address Reset value Name Description Rx-DES/3DES Register Map (Rx side) Base + 0x00 0x0000_0040 TDES_Rx_CTRL DES/3DES Rx Contrl / Status Reg. Base + 0x10 0x0000_0000 TDES_Rx_KEY1_0 DES/3DES Rx Key Input Reg. 1_0...
Page 343 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR Table 6 SHA-1/PRNG Register Map Address Reset value Name Description Rx-SHA-1/PRNG Register Map (Rx side) Base + 0x00 0x0000_0000 HASH_CONTROL Hash engine control Reg. Base + 0x04 0x0000_0000 HASH_DATA HASH data or HMAC Key Input Reg.
Page 344 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM HASH_MIDOUT[63:32] Base + 0x68 0x0000_0000 HASH_MIDOUT_04 HASH_MIDOUT[31:0] Base + 0x6C 0x0000_0000 HASH_MIDOUT_05 Base + 0x70 0x0000_0000 HASH_IV_01 HASH initial value 01 Base + 0x74 0x0000_0000 HASH_IV_02 HASH initial value 02 Base + 0x78 0x0000_0000 HASH_IV_03...
Page 345 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR DMA & INTERRUPT CONTROL MODULE SECURITY SUB-SYSTEM DMA & INTERRUPT REGISTER Register Address Description Reset Value DnI_Cfg 0x7D00_0000 R/W DMA and interrupt configuration Control & Status Reg. 0x0000_0000 DnI_Cfg Description Initial State WrPrivMismatch [31] SFR Write Access Privilege Mismatch Status bit. If set to ‘1’, SFR Write Access Privilege Mismatch is occurred.
Page 346 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM SECURITY SUB-SYSTEM RX FIFO MODULE FIFO-RX CONTROL REGISTER Register Address Description Reset Value FRx_Ctrl 0x7D40_0000 FIFO-Rx Control/Status Reg. (Only MSB 16-bit readable) 0x0420_0000 FRx_Ctrl Description Initial State Sets to 1 if write access to FIFO-Rx has resulted in a...
Page 347 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR FIFO-RX MESSAGE LENGTH REGISTER Register Address Description Reset Value FRx_MLen 0x7D40_0004 R/W FIFO-Rx Message Length Reg. 0x0000_0000 FRx_MLen Description Initial State FRx_MLen [31:0] Message Length in word (32-bit) unit. 0x0000_0000 Resets to its reset value when FRx_Reset field of FRx_Ctrl register is set.
Page 348 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM FIFO-RX MESSAGE LENGTH COUNTER Register Address Description Reset Value FRx_MLenCnt 0x7D40_0010 R/W FIFO-Rx Message Count Reg. (Number of words left) 0x0000_0000 FRx_MLenCnt Description Initial State FRx_MLenCnt [31:0] Number of words left for transfer. 0x0000_0000 FIFO-RX WRITE BUFFER...
Page 349 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM TX FIFO MODULE FIFO-TX CONTROL REGISTER Register Address Description Reset Value FTx_Ctrl 0x7D80_0000 R/W FIFO-Tx Control/Status Reg. (Only MSB 16-bit readable) 0x0400_2000 FTx_Ctrl Description Initial State Sets to 1 if write access to FIFO-Tx has resulted in a privilege...
Page 350 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM FIFO-TX MESSAGE LENGTH REGISTER Register Address Description Reset Value FTx_MLen 0x7D80_0004 R/W FIFO-Tx Message Length Reg. 0x0000_0000 FTx_MLen Description Initial State FTx_MLen [31:0] Message Length in word(32-bit) unit. 0x0000_0000 Resets to its reset value when FTx_Reset field of FTx_Ctrl register is set.
Page 351 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR FIFO-TX READ BUFFER Register Address Description Reset Value 0x7D80_0040 FIFO-Tx read buffer (32-word ) 0x0000_0000 Note: This address is for CPU access. 0x7D80_007C FTx_RdBuf 0x7DA0_0040 FIFO-Tx read buffer (32-word ) Note: This address is for SDMA1(Security DMA 1). You...
Page 352 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM SECURITY SUB-SYSTEM AES MODULE AES_CTRL Register Address Description Reset Value AES_Rx_CTRL 0x7D10_0000 R/W AES Control / Status Register 0x0000_0200 SKEY_IDx Description Initial State SFR Write Access Privilege Mismatch Status bit. If set to ‘1’, WrPrivMismatch [31] SFR Write Access Privilege Mismatch is occurred.
Page 353 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR AES_RX_DIN_01 ~ AES_RX_DIN_01 Register Address Description Reset Value AES_Rx_DIN_01 0x7D10_0010 R/W AES Data Input Register 01 (Least Significant) 0x0000_0000 AES_Rx_DIN_02 0x7D10_0014 R/W AES Data Input Register 02 (Least Significant) 0x0000_0000 AES_Rx_DIN_03 0x7D10_0018 R/W AES Data Input Register 02 (Least Significant)
Page 354 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM AES_RX_KEY_01 ~ AES_RX_KEY_08 Register Address Description Reset Value AES_Rx_KEY_01 0x7D10_0080 R/W AES Key Input Register 01 (Least Significant) 0x0000_0000 AES_Rx_KEY_02 0x7D10_0084 R/W AES Key Input Register 02 (Least Significant) 0x0000_0000 AES_Rx_KEY_03 0x7D10_0088 R/W AES Key Input Register 03 (Least Significant)
Page 355 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM DES/3DES MODULE TDES_RX_CTRL Register Address Description Reset Value TDES_Rx_CTRL 0x7D20_0000 R/W TDES control / status register 0x0000_0040 TDES_Rx_CTRL Description Initial State SFR Write Access Privilege Mismatch Status bit. If set to ‘1’, WrPrivMismatch [31] SFR Write Access Privilege Mismatch is occurred.
Page 356 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM TDES_RX_KEY1_0 Register Address Description Reset Value TDES_Rx_KEY1_0 0x7D20_0010 R/W TDES Key Input Register 1_0 (Least Significant) 0x0000_0000 TDES_Rx_KEY1_1 0x7D20_0014 R/W TDES Key Input Register 1_1 (Least Significant) 0x0000_0000 TDES_Rx_KEY2_0 0x7D20_0018 R/W TDES Key Input Register 2_0 (Least Significant)
Page 357 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR TDES_RX_IV_0 / TDES_RX_IV_1 Register Address Description Reset Value TDES_Rx_IV_0 0x7D20_0050 R/W TDES IV Input Register 0 0x0000_0000 TDES_Rx_IV_1 0x7D20_0054 R/W TDES IV Input Register 1 0x0000_0000 TDES_Rx_IV Description Initial State TDES 1 and 2 32bit IV Input Register...
Page 358 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM SECURITY SUB-SYSTEM SHA-1/PRNG MODULE HASH_CONTROL Register Address Description Reset Value HASH_CONTROL 0x7D30_0000 R/W Hash engine control register 0x0000_0000 HASH_CONTROL Description Initial State Reserved [31:9] Reserved 0x0000_00 Use arbitrary IV instead of SHA-1 constants USE_IV 0: constants...
Page 359 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR SEED_DATA_01 ~ SEED_DATA_10 Register Address Description Reset Value SEED_DATA_01 0x7D30_0008 R/W PRNG seed data 1 ([31:0]) 0x0000_0000 SEED_DATA_02 0x7D30_000C R/W PRNG seed data 2 [63:32] 0x0000_0000 SEED_DATA_03 0x7D30_0010 R/W PRNG seed data 3 [95:64] 0x0000_0000...
Page 360 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM HASH_OUTPUT_01 (PRNG_OUTPUT_01) ~ HASH_OUTPUT_10 (PRNG_OUTPUT_10) Register Address Description Reset Value HASH_OUTPUT_01 0x7D30_0034 Hash output (01) or PRNG output [31:1] 0x0000_0000 HASH_OUTPUT_02 0x7D30_0038 Hash output (02) or PRNG output [63:32] 0x0000_0000 HASH_OUTPUT_03 0x7D30_003C Hash output (03) or PRNG output [95:64]...
Page 361 SECURITY SUB-SYSTEM S3C6400X RISC MICROPROCESSOR HASH_MIDOUT_01 ~ HASH_MIDOUT_05 Register Address Description Reset Value HASH_MIDOUT_01 0x7D30_005C HASH_MIDOUT[159:128] 0x0000_0000 HASH_MIDOUT[127:96] HASH_MIDOUT_02 0x7D30_0060 0x0000_0000 HASH_MIDOUT[95:64] HASH_MIDOUT_03 0x7D30_0064 0x0000_0000 HASH_MIDOUT[63:32] HASH_MIDOUT_04 0x7D30_0068 0x0000_0000 HASH_MIDOUT[31:0] HASH_MIDOUT_05 0x7D30_006C 0x0000_0000 HASH_MIDOUT_01 0x7D70_005C HASH_MIDOUT[159:128] 0x0000_0000 HASH_MIDOUT[127:96] HASH_MIDOUT_02 0x7D70_0060...
Page 362 S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM PRE_MSG_LENGTH_01 / PRE_MSG_LENGTH_02 Register Address Description Reset Value PRE_MSG_LENGTH_01 0x7D70_0084 R/W PRE_MSG_LENGTH [63:32] 0x0000_0000 PRE_MSG_LENGTH_02 0x7D70_0088 R/W PRE_MSG_LENGTH [31:0] 0x0000_0000 PRE_MSG_LENGTH Description Initial State PRE_MSG_LENGTH [31:0] PRE_MSG_LENGTH 0x0000_0000 Preliminary product information describe products that are in development, 13-25 for which full characterization data and associated errata are not yet available.
Page 363 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER DISPLAY CONTROLLER OVERVIEW The Overlay/Display controller includes logic for transferring image data from a local bus of the POST Processor or a video buffer located in system memory to an external LCD driver interface. LCD driver interface has three kinds of interface, i.e.
Page 364 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR FEATURES The FIMD supports the following: Video Output Interface RGB IF I80 CPU Interface TV Encoder Interface (NTSC, PAL standard) PIP (OSD) function Supports 8-BPP (bit per pixel) palletized color Supports 16-BPP non-palletized color Supports unpacked 18-BPP non-palletized color...
Page 365 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER Palette/Look-up table 256 x 25(ARGB) bits palette (2ea for Window 0, Window1) 16(entry) x 16 bits Look-up table for Window 2 16(entry) x 16 bits Look-up table for Window 3 4(entry) x 16 bits Look-up table for Window 4...
Page 366 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR FUNCTIONAL DESCRIPTION BRIEF OF THE SUB-BLOCK The display controller consists of a VSFR, VDMA, VPRCS, VTIME, and video clock generator. The VSFR includes programmable register sets and two-256x 25 palette memories. These are used to configure the display controller.
Page 367 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER Figure 14-2. Block diagram of the Data Flow Interface Display controller supports 2 types of display device. One type is the conventional RGB-interface which uses RGB data, Vertical/horizontal sync, data valid signal and data sync clock. The Second type is I80 CPU Interface which uses address, data, chip select, read/write control and register/status indicating signal.
Page 368 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR Overview of the Color Data RGB Data format The display controller requests the specified memory format of frame buffer. The next table shows some examples of each display mode. 25BPP display (A888) (BSWP = 0, HWSWP = 0)
Page 369 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER 24BPP display (A887) (BSWP = 0, HWSWP = 0) D[31:24] D[23] D[22:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel Note 1. AEN : Transparency value selection bit AEN = 0 : Select ALPHA0 AEN = 1 : Select ALPHA1 If per-pixel blending is set, then this pixel would be blended with alpha value selected by AEN.
Page 370 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR 24BPP display (888) (BSWP = 0, HWSWP = 0) D[31:24] D[23:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel Note: 1. D[23:16] = Red data, D[15:8] = Green data, D[7:0] = Blue data Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 371 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER 19BPP display (A666) (BSWP = 0, HWSWP = 0) D[31:19] D[18] D[17:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel Note 1. AEN : Transparency value selection bit AEN = 0 : Select ALPHA0 AEN = 1 : Select ALPHA1 If per-pixel blending is set, then this pixel would be blended with alpha value selected by AEN.
Page 372 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR 18BPP display (666) (BSWP = 0, HWSWP = 0) D[31:18] D[17:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel ..LCD Panel Note: 1. D[17:12] = Red data, D[11:6] = Green data, D[5:0] = Blue data Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 373 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER 16BPP display (A555) (BSWP = 0, HWSWP = 0) D[31] D[30:16] D[15] D[14:0] 000H AEN1 AEN2 004H AEN3 AEN4 008H AEN5 AEN6 (BSWP = 0, HWSWP = 1) [31] D[30:16] D[15] D[14:0] 000H AEN2 AEN1...
Page 374 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR 16BPP display (1555) (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H 004H 008H (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H 004H 008H ..LCD Panel Note: 1. {D[14:10], D[15] } = Red data, {D[9:5], D[15] } = Green data, {D[4:0], D[15]}= Blue data Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 375 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER 16BPP display (565) (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H 004H 008H (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H 004H 008H ..LCD Panel Note: 1. D[15:11] = Red data, D[10:5] = Green data, D[4:0] = Blue data...
Page 376 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR 8BPP display(Palette) (BSWP = 0, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H 004H 008H (BSWP = 1, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H 004H 008H ..P10 P11 P12 LCD Panel Note: 1.
Page 377 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER 4BPP display(Palette) (BSWP = 0, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H 004H 008H (BSWP = 1, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H 004H...
Page 378 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR 2BPP display(Palette) (BSWP = 0, HWSWP = 0) [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] 000H 004H 008H [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 000H 004H 008H Note: 1. If ALPHAPAL is enabled, then the MSB of Palette memory is acting as a AEN bit.
Page 379 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER Palette usage Palette Configuration and Format Control The display controller can support the 256 color palette for various selection of color mapping. The user can select 256 colors from the 25-bit colors through these four formats.
Page 380 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR Table 14-2. 16BPP(A:5:5:5) Palette Data Format INDE 9 8 7 6 5 4 3 2 1 0 X\Bit Pos. - … … … … … … … … … … … … … … … …...
Page 381 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER WINDOW BLENDING Overview The main function of the VPRCS module is window blending. Display controller has 5 window layers and the details are described below. For example, System can use win0 as a OS window, full TV screen window or etc., win1 as a small (next channel ) TV screen with win2 as a menu, win3 as a caption, win 4 as a channel information.
Page 382 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR WinOut(R) = Win0123(R) x Beta + Win4(R) x Alpha WinOut(G) = Win0123(G) x Beta + Win4(G) x Alpha WinOut(B) = Win0123(B) x Beta + Win4(B) x Alpha Where, if A bit is set then AR1 = Window 1’s Red blending factor (ALPHA1_R@VIDOSD1C) AR2 = Window 2’s Red blending factor (ALPHA1_R@VIDOSD2C)
Page 383 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER BLENDING DIAGRAM/DETAILS Display controller can blend 5 Layer for only one pixel at the same time. The Blending factor, alpha value is controlled by ALPHA0_R,ALPHA0_G,ALPHA0_B, ALPHA1_R,ALPHA1_G,ALPHA1_B register, which are implemented for each window layer and color(R,G,B). The illustration below is described as the example of the R (Red) output using ALPHA_R value of each window.
Page 384 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR Table 14-3. Blending User’s Table ALPHA_SEL[1] value @ WINCON1/2/3/4 ‘0’ ‘1’ ‘0’ Plane blending using ALPHA0 Plane blending using ALPAH1 Pixel blending selected by AEN AEN value @ Frame Buffer ‘0’ ‘1’ Using ALPHA0 Using ALPHA1...
Page 385 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER COLOR-KEY FUNCTION The display controller supports color-key function for the various effect of image mapping. Color image of OSD layer, which is specified by COLOR-KEY register, will be substituted by back-ground image for special functionality. It will be substituted as cursor image or pre-view image of the camera.
Page 386 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR VTIME CONTROLLER OPERATION VTIME is mainly divided into to blocks. One is VTIME_RGB_TV for RGB interface and TV Encoder Interface timing control. The other is for I80 CPU interface timing control. RGB Interface Controller The VTIME generates the control signals such as, RGB_VSYNC, RGB_HSYNC, RGB_VDEN and RGB_VCLK signal for RGB interface.
Page 387 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER The RGB_HSYNC and RGB_VSYNC signal is configured by VSYNC, VBPD, VFPD, HSYNC, HBPD, HFPD, HOZVAL and LINEVAL. For more information refer to the Figure 14-8. The frame rate is RGB_VSYNC signal frequency. The frame rate is related with the field of VSYNC, VBPD, VFPD, LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, CLKVAL registers.
Page 388 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR LDI_CMD0 0x1, LDI_CMD1 0x32, LDI_CMD2 0x2, LDI_CMD3 0x8f, LDI_CMD4 0x4, LDI_CMD5 0x99 CMD0_EN 0x2, CMD1_EN 0x2, CMD2_EN 0x2, CMD3_EN 0x2, CMD4_EN 0x2, CMD5_EN CMD0_RS 0x1, CMD1_RS 0x0, CMD2_RS 0x1, CMD3_RS 0x0, CMD4_RS 0x1, CMD5_RS AUTO_CMD_RATE Note: 1).
Page 389 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER Command Setting Example) ** CMD0_EN = 2’b10, CMD1_EN = 2’b11, CMD2_EN = 2’b01, CMD3_EN = 2’b11, CMD4_EN = 2’b01 (Auto Command : CMD0, CMD1, CMD3, Normal Command : CMD1, CMD2, CMD3, CMD4) ** AUTO_COMMAND_RATE = 4’b0010 (per 4 frames)
Page 390 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR VIRTUAL DISPLAY The display controller supports the hardware horizontal or vertical scrolling. If the screen is scrolled, you must change the fields of LCDBASEU and LCDBASEL registers (For more information refer to Figure 14-7). You must not change the values of PAGEWIDTH and OFFSIZE.
Page 391 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER RGB INTERFACE SPEC Signals Table 14-5. RGB Interface Pin Description Name Type Source/Destination Description RGB_HSYNC Output Horizontal Sync. Signal RGB_VSYNC Output Vertical Sync. Signal RGB_VCLK Output LCD Video Clock RGB_VDEN Output Data Enable RGB_VD[23:0] Output RGB data output.
Page 392 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR LCD I80 CPU INTERFACE Signals Table 14-6. I80 CPU Interface Pin Description Name Type Source/Destination Description SYS_VDIN[17:0] Video Mux Video Data Input SYS_VDOUT[17:0] Video Mux Video Data Output SYS_CS0 Output Video Mux Chip select for LCD0...
Page 393 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER LCD DATA PIN MAP Table 14-7. Parallel/Serial RGB, CPU I/F Data Pin Map ( - : Not Used) Parallel RGB Serial RGB I80 CPU I/F (Parallel) 24BPP 18BPP 16BPP 24BPP 16BPP 18BPP 16BPP (888) (666)
Page 394 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR VD[0] B[0] B[0] B[0] LCD NORMAL/BY-PASS MODE SELECTION The external modem or MCU can access the system interface LCD Panel through the by-pass. After reset, the initial output path of LCD controller is by-pass like described in below figure 14-10. In order to operate in the normal display mode (RGB or CPU I/F), SEL_BYPASS[3] value @ 0x7410800C must be set as ‘0’(normal mode)
Page 395 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER PROGRAMMER’S MODEL OVERVIEW The following registers are used to configure display controller: 1. MOFPCON: SEL_BYPASS[3] value @ 0x7410800C must be set as ‘0’(normal mode) instead of ‘1’(by-pass mode). 2. SPCON: LCD_SEL[1:0] value @ 0x7F0081A0 must be set as ‘00’ to use Host I/F Style or as ‘01’ to use RGB I/F Style 3.
Page 396 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR WINCON4 0x77100030 Window control 4 register 0x0000_0000 VIDOSD0A 0x77100040 Video Window 0’s position control register 0x0000_0000 VIDOSD0B 0x77100044 Video Window 0’s position control register 0x0000_0000 VIDOSD0C 0x77100048 Video Window 0’s position control register 0x0000_0000 VIDOSD1A 0x77100050 Video Window 1’s position control register...
Page 397 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER W1KEYCON0 0x77100140 Color key control register 0x0000_0000 W1KEYCON1 0x77100144 Color key value ( transparent value) register 0x0000_0000 W2KEYCON0 0x77100148 Color key control register 0x0000_0000 W2KEYCON1 0x7710014C Color key value (transparent value) register 0x0000_0000 W3KEYCON0 0x77100150...
Page 398 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR LDI_CMD7 0x7710029C I80 Interface LDI Command 7 0x0000_0000 LDI_CMD8 0x771002A0 I80 Interface LDI Command 8 0x0000_0000 LDI_CMD9 0x771002A4 I80 Interface LDI Command 9 0x0000_0000 LDI_CMD10 0x771002A8 I80 Interface LDI Command 10 0x0000_0000 LDI_CMD11 0x771002AC I80 Interface LDI Command 11...
Page 399 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER [28] Reserved (Must be zero) VIDOUT [27:26] It determines the output format of Video Controller 00: RGB I/F 01: TV Encoder Interface 10: I80 CPU I/F for LDI0 11: I80 CPU I/F for LDI1 L1_DATA16 [25:23] Select the mode of output data format of I80 CPU I/F (LDI1.)
Page 400 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR 2. Video Clock Source is selected by CLKSEL_F register Reserved CLKDIR Select the clock source as direct or divide using CLKVAL_F register 0 = Direct clock (frequency of VCLK = frequency of Clock source) 1 = Divided by CLKVAL_F...
Page 401 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER edge IHSYNC This bit indicates the HSYNC pulse polarity. 0 = normal 1 = inverted IVSYNC This bit indicates the VSYNC pulse polarity. 0 = normal 1 = inverted IVDEN This bit indicates the VDEN signal polarity.
Page 402 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR VIDEO Time Control 2 Register Register Address Description Reset Value VIDTCON2 0x77100018 Video time control 2 register 0x0000_0000 VIDTCON2 Description Initial state LINEVAL [21:11] These bits determine the vertical size of display HOZVAL [10:0] These bits determine the horizontal size of display Note.
Page 403 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER It indicates the input color space of source image. (Only for ‘ENLOCALl’ enable) InRGB [13] 0: RGB 1: YCbCr reserved [12:11] Should be ‘0’ BURSTLEN [10:9] DMA’s Burst Maximum Length selection: 00: 16 word– burst 01: 8 word–...
Page 404 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR LOCALSEL [23] Select Local Path Source 0 : TV scaler (FIFO Out) 1 : Camera preview local IF Note. When the camera preview local IF is selected, there is a constraint that the source of camera preview local IF must be memory not external camera.
Page 405 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER 0010 = 4 BPP 0011 = 8 BPP ( palletized ) 0100 = 8 BPP ( non-palletized, A: 1-R:2-G:3-B:2 ) 0101 = 16 BPP ( non-palletized, R:5-G:6-B:5 ) 0110 = 16 BPP ( non-palletized, A:1-R:5-G:5-B:5 )
Page 406 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR LOCALSEL [23] Select Local Path Source 0 : TV scaler (FIFO Out) 1 : Camera codec local IF Note. When the camera codec local IF is selected, there is a constraint that the source of camera codec local IF must be memory not external camera.
Page 407 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER 1001 = unpacked 18 BPP ( non-palletized, A:1-R:6-G:6-B:5 ) 1010 = unpacked 19 BPP ( non-palletized, A:1-R:6-G:6-B:6 ) 1011 = unpacked 24 BPP ( non-palletized R:8-G:8-B:8 ) 1100 = unpacked 24 BPP ( non-palletized A:1-R:8-G:8-B:7 )
Page 408 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR 1 = Per pixel blending BPPMODE_F [5:2] Select the BPP (Bits Per Pixel) mode Window image. 0000 = 1 BPP (LUT ) 0001 = 2 BPP (LUT ) 0010 = 4 BPP (LUT ) 0011 = reserved...
Page 409 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER BYTSWP [17] Byte swaps control bit. 0 = Swap Disable 1 = Swap Enable HAWSWP [16] Half-Word swap control bit. 0 = Swap Disable 1 = Swap Enable Reserved [15:11] Must be ‘0’ BURSTLEN [10:9] DMA’s Burst Maximum Length selection :...
Page 410 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR ENWIN_F Video output and the logic immediately enable/disable. 0 = Disable the video output and the VIDEO control signal. 1 = Enable the video output and the VIDEO control signal. Window 0 Position Control A Register...
Page 411 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER VIDOSD0C Description initial state [25:24] Reserved OSDSIZE [23:0] Window Size Eq. Height * Width (Number of Word) Note. Set filed value for YUV if (TV Encoder IF) Window 1 Position Control A Register Register Address...
Page 412 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR Window 1 Position Control C Register Register Address Description Reset Value VIDOSD1C 0x77100058 Video Window 1’s alpha control register VIDOSD1C Description initial state [24] Reserved ALPHA0_R [23:20] Red Alpha value(case AEN == 0) ALPHA0_G [19:16]...
Page 413 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER original screen y coordinate. And the original screen y coordinate MUST be even value.) Window 2 Position Control B Register Register Address Description Reset Value VIDOSD2B 0x77100064 Video Window 2’s position control register VIDOSD2B Description...
Page 414 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR Window 2 Position Control D Register Register Address Description Reset Value VIDOSD2D 0x7710006C Video Window 0’s Size control register VIDOSD2D Description initial state [25:24] Reserved OSDSIZE [23:0] Window Size Eq. Height * Width(Number of Word) Note.
Page 415 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER Note. Registers must have word boundary X position. So, 24 BPP mode must have X position by 1 pixel. ( ex, X = 0,1,2,3….) 16 BPP mode must have X position by 2 pixel. ( ex, X = 0,2,4,6….) 8 BPP mode must have X position by 4 pixel.
Page 416 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR Window 4 Position Control B Register Register Address Description Reset Value VIDOSD4B 0x77100084 Video Window 4’s position control register VIDOSD4B Description initial state OSD_RightBotX_F [21:11] Horizontal screen coordinate for right bottom pixel of OSD image...
Page 417 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER FRAME Buffer Address 0 Register Register Address Description Reset Value VIDW00ADD0B0 0x771000A0 R/W Window 0’s buffer start address register, buffer 0 VIDW00ADD0B1 0x771000A4 R/W Window 0’s buffer start address register, buffer 1 VIDW01ADD0B0 0x771000A8 R/W Window 1’s buffer start address register, buffer 0...
Page 418 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR FRAME Buffer Address 2 Register Register Address Description Reset Value VIDW00ADD2 0x77100100 Window 0’s buffer size register VIDW01ADD2 0x77100104 Window 1’s buffer size register VIDW02ADD2 0x77100108 Window 2’s buffer size register VIDW03ADD2 0x7710010C Window 3’s buffer size register...
Page 419 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER 00 = None 01 = BACK Porch 10 = VSYNC 11 = FRONT Porch INTFRMEN [12] Video Frame interrupts Enable control bit. 0 = Video Frame Interrupt Disable 1 = Video Frame Interrupt Enable FIFOSEL...
Page 420 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR INTFIFOPEND FIFO Level interrupt. To clear this bit, write “1” . 0 = The interrupt has not been requested 1 = FIFO empty status has asserted the interrupt request Win1 Color Key 0 Register Register...
Page 421 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER W2KEYCON0 Description Initial state KEYBLEN [26] Color Key (Chroma key ) Enable control 0 = disable ( blending operation disable ) 1 = Blending using ALPHA0_x for non-key area, ALPHA1_x for key area (x=R, G, B)
Page 422 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR pixel from back-ground image is displayed ( only in OSD area) 1 = If the pixel value of back-ground matches with COLVAL, the pixel from fore-ground image is displayed ( only in OSD area) COMPKEY [23:0] Each bit is correspond to the COLVAL[23:0].
Page 423 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER WIN4 Color key 1 Register Register Address Description Reset Value W4KEYCON1 0x7710015C Color key value ( transparent value) register 0x0000_000 W4KEYCON1 Description Initial state COLVAL [23:0] Color key value for the transparent pixel effect. Note. COLVAL and COMPKEY use 24bit color data at all BPP mode.
Page 424 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR Dithering Control 1 Register Register Address Description Reset Value DITHMODE 0x77100170 Dithering mode register. 0x00000 DITHMODE Description Initial state Should be zero RDithPos [6:5] Red Dither bit control 00 : 8bit 01 : 6bit 10 : 5bit...
Page 425 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER WIN1MAP Description Initial state MAPCOLEN_ [24] Window’s color mapping control bit . If this bit is enabled then Video DMA will stop, and MAPCOLOR will be appear on back-ground image instead of original image. 0 = disable...
Page 426 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR WIN4MAP Description Initial state MAPCOLEN_F [24] Window’s color mapping control bit . If this bit is enabled then Video DMA will stop, and MAPCOLOR will be appear on back-ground image instead of original image. 0 = disable...
Page 427 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER 010 = 19 bit ( A:6:6:6 ) 011 = 18 bit ( A:6:6:5 ) 100 = 18 bit ( 6:6:6 ) 101 = 16 bit ( A:5:5:5 ) 110 = 16 bit ( 5:6:5 )
Page 428 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR LCD_WR_ACT [11:8] Numbers of clock cycles for the active period of the chip select enable. LCD_WR _HOLD [7:4] Numbers of clock cycles for the active period of the chip select disable to the write signal disable.
Page 429 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER … 1111 : per 30 Frames LCD I80 Interface Command Control 0 Register Address Description Reset Value LDI_CMDCON0 0x771001D0 I80 System Interface Command Control 0 0x00000 LDI_CMDCO Description Initial state Reserved [31:24] CMD11_EN [23:22] 00 : Disable...
Page 430 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR CMD6_EN [13:12] 00 : Disable 01 : Normal Command Enable 10 : Auto Command Enable 11 : Normal and Auto Command Enable CMD5_EN [11:10] 00 : Disable 01 : Normal Command Enable 10 : Auto Command Enable...
Page 431 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER LCD I80 Interface Command Control 1 Register Address Description Reset Value LDI_CMDCO 0x771001D4 I80 System Interface Command Control 1 0x00000 LDI_CMDCO Description Initial state [31:10] Reserved CMD11_RS [11] Command 11 RS control CMD10_RS [10] Command 10 RS control...
Page 432 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR SYS_nCS1_CON LCD I80 System Interface nCS1 (sub) Signal control 0: Disable (High) 1: Enable (Low) SYS_nOE_CON LCD I80 System Interface nOE Signal control 0: Disable (High) 1: Enable (Low) SYS_nWE_CON LCD I80 System Interface nWE Signal control...
Page 433 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER LCD I80 Interface Command Register Address Description Reset Value LDI_CMD0 0x77100280 I80 Interface Command 0 LDI_CMD1 0x77100284 I80 Interface Command 1 LDI_CMD2 0x77100288 I80 Interface Command 2 LDI_CMD3 0x7710028c I80 Interface Command 3 LDI_CMD4 0x77100290...
Page 434 DISPLAY CONTROLLER S3C6400X RISC MICROPROCESSOR W3PDATAxx Description Initial State ODD_VAL [31:16] Lut Value register EVEN_VAL [15:0] Lut Value register Window 3’s Palette Data Register Address Description Reset Value W3PDATA01 0x77100320 Window 3 Palette Data of the Index 0,1 W3PDATA23 0x77100324...
Page 435 S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER WIN1 Palette Ram Access Address (not SFR) Index Address Description Reset Value 0x77100800 Window 1 Palette entry 0 address undefined 0x77100804 Window 1 Palette entry 1 address undefined 0x77100BFC Window 1 Palette entry 255 -address...
Page 436 S3C6400X RISC MICROPROCESSOR POST PROCESSOR POST PROCESSOR VER2.5 This chapter describes the functions and usage of the Postprocessor interface of the S3C6400. OVERVIEW The Post processor administers the video/graphic scale, video format conversion and color space conversion. It is composed of Data-Path, DMA controller and Register files as shown in the Figure 15-1.
Page 437 POST PROCESSOR S3C6400X RISC MICROPROCESSOR OVERALL FEATURES AMBA AHB v2.0 compatible interface Dedicated DMA with offset address 3 Channel scaling pipelines for video/graphic scaling up/down or zooming in/out Video input format: 420, 422 format Graphic input format: 16-bit (565format) or 24-bit...
Page 438 S3C6400X RISC MICROPROCESSOR POST PROCESSOR A Source and Destination Image Data Format In FIMV POST Processor, two output modes such as DMA mode and FIFO mode are available as shown in the following Figure 15-2. In FIFO mode (if LCDPathEnable = 1, For more information refer to chapter 6. Register File List), destination image is transferred to the FIFO in display controller (or some other IP with FIFO interface) without additional memory bandwidth such as POST-to-Memory and Memory-to-Display Controller.
Page 439 POST PROCESSOR S3C6400X RISC MICROPROCESSOR 2.1 DMA Mode Operation Various source and destination image formats can be selected according to the mode configuration as described in Table 15-1 a). Source image format is one of the following YCbCr420, YCbCr422, RGB16-bit (565format) and RGB 24-bit format.
Page 440 S3C6400X RISC MICROPROCESSOR POST PROCESSOR Table 15-1 a). Mode configuration for video/graphic source format and the corresponding data format MODE[8] MODE[3] MODE[2] MODE[1] MODE[15][0] Description SRC420 InRGB INTER- InRGB InYCbCr Data Format Video/Graphic LEAVE Format Format Format in Fig15-3 and 4...
Page 441 POST PROCESSOR S3C6400X RISC MICROPROCESSOR WORD WORD Y Cb Y Cr Video Data Cb Cb Cb Cb Cb Y Cr Y 1 Frame 1 Frame Cr Cr Cr Cr Pixel Pixel Memory Space Memory Space (a) Non-Interleaving (b) Interleaving Figure 15-3 Data format stored in external...
Page 442 S3C6400X RISC MICROPROCESSOR POST PROCESSOR 2.2 FIFO Mode Operation Output data format is determined by MODE[18] as described in Table 15-1 b). The output data format is fixed to 30-bit data, 10-bit per each component RGB or YCbCr444. The other specific mode configuration signals mentioned in Table 15-1 b) are ignored if ExtFIFOIn or LCDPathEnable is set to “1”.
Page 443 POST PROCESSOR S3C6400X RISC MICROPROCESSOR such a way that the number of horizontal pixel can be represented by kn where n = 1,2,3, … and k = 1 / 2 / 8 for 24bppRGB / 16bppRGB / YCbCr420 image, respectively. Also SRC_Width must be multiples of 4 PreScale_H_Ratio and SRC_Height must be multiple of PreScale_V_Ratio.
Page 444 S3C6400X RISC MICROPROCESSOR POST PROCESSOR else if (SRC_Height >= 16 × DST_Height) { PreScale_V_Ratio = 16; V_Shift = 4; } else if (SRC_Height >= 8 × DST_Height) { PreScale_V_Ratio = 8; V_Shift = 3; } else if (SRC_Height >= 4 × DST_Height) { PreScale_V_Ratio = 4; V_Shift = 2; } else if (SRC_Height >= 2 ×...
Page 445 POST PROCESSOR S3C6400X RISC MICROPROCESSOR 4. DMA operation of Source and Destination Image There are three address categories such as start address, end address and offset address for DMA operation. Each address category consists of three source address components of Y/Cb/Cr and three destination address component of RGB/oCb/oCr.
Page 446 S3C6400X RISC MICROPROCESSOR POST PROCESSOR 4.1 Start address Start address of ADDRStart_Y/Cb/Cr/RGB/oCb/oCr points the first word address where the corresponding component of Y/Cb/Cr/RGB/oCb/oCr is read or written. Each one must be aligned with word boundary (i.e. ADDRStart_X[1:0] = 00). ADDRStart_Cb and ADDRStart_Cr are valid only for the YCbCr420 source image format.
Page 447 POST PROCESSOR S3C6400X RISC MICROPROCESSOR Where, Offset_Y/Cb/Cr/RGB = Memory size for offset per a horizontal line = Number of pixel (or sample) in horizontal offset × ByteSize_Per_Pixel (or Sample) ByteSize_Per_Pixel = 1 for YCbCr420 2 for 16-bit RGB and YcbCr422...
Page 448 S3C6400X RISC MICROPROCESSOR POST PROCESSOR Offset address is used for the following two situations. One is to fetch some parts of source image in order to zoom in/out as shown in Figure 15-7 (a). The other is to restore destination image for PIP (picture-in-picture) applications as shown in Figure 15-7 (b).
Page 449 POST PROCESSOR S3C6400X RISC MICROPROCESSOR 5. Frame Management of POST Processor 5.1 Per Frame Management Mode Per frame management of POST-Processor are controlled by two control register such as POSTENVID and POSTINT as shown in Figure 15-8. “POSTENVID” triggers the operation of POST PROCESSOR. It is automatically de-asserted when all operations of the given frame are completed.
Page 450 S3C6400X RISC MICROPROCESSOR POST PROCESSOR 6. Register File Lists Register Address Description Reset Value MODE 0x77000000 R/W Mode Register 0x00070B12 PreScale_Ratio 0x77000004 R/W Pre-Scale ratio for vertical and horizontal PreScaleImgSize 0x77000008 R/W Pre-Scaled image size SRCImgSize 0x7700000C R/W Source image size...
Page 451 POST PROCESSOR S3C6400X RISC MICROPROCESSOR RESERVED 0x77000050 - NxtADDRStart_Y 0x77000054 R/W Next Frame (Buffer 1) DMA Start address for 0x20000000 source Y or RGB component NxtADDRStart_Cb 0x77000058 R/W Next Frame (Buffer 1) DMA Start address for 0x20000000 source Cb component...
Page 452 S3C6400X RISC MICROPROCESSOR POST PROCESSOR NxtADDREnd_oCr 0x77000098 R/W Next Frame DMA (Buffer 1) End address for 0x20006300 destination Cr component POSTENVID 0x7700009C R/W Enable Video Processing. MODE_2 0x770000A0 R/W Mode Register 2 Preliminary product information describe products that are in development, 15-17 for which full characterization data and associated errata are not yet available.
Page 453 POST PROCESSOR S3C6400X RISC MICROPROCESSOR MODE Control Register Register Address Description Reset Value Mode Register [31:0] 0x00070B12 MODE 0x77000000 MODE Description Initial State reserved [31] Must be “0” CLKVALUP [30] Select CLKVAL_F update timing control 0 = always 1 = start of a frame (only once per frame)
Page 454 S3C6400X RISC MICROPROCESSOR POST PROCESSOR AutoLoadEnable [14] AutoLoadEnalbe. 0 for Per Frame mode and 1 for Free Run mode LCDPathEnable [13] Out FIFO Mode Enable. 1 for FIFO mode and 0 for DMA mode Interlace [12] Output scan method selection register only when FIFO mode (LCDPathEnable =1).
Page 455 POST PROCESSOR S3C6400X RISC MICROPROCESSOR Figure 15-10 Internal clock scheme Block Diagram Preliminary product information describe products that are in development, 15-20 for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 456 S3C6400X RISC MICROPROCESSOR POST PROCESSOR Pre-Scale Ratio Register Register Address Description Reset Value Pre-Scale ratio for vertical and horizontal. PreScale_Ratio 0x77000004 PreScale_Ratio Description Initial State PreScale_V_Ratio [13:7] Pre-scale ratio for vertical direction (For more information refer to chapter 15-3) PreScale_H_Ratio...
Page 457 POST PROCESSOR S3C6400X RISC MICROPROCESSOR Source Image Size Register Register Address Description Reset Value Source image size SRCImgSize 0x7700000C SRCImgSize Description Initial State SRCHeight [23:12] Source image height (For more information refer to chapter 15-3) SRCWidth [11:0] Source image width (For more information refer to chapter 15-3)
Page 458 S3C6400X RISC MICROPROCESSOR POST PROCESSOR Destination Image Size Register Register Address Description Reset Value DSTImgSize 0x77000018 Destination image size SRCImgSize Description Initial State DSTHeight [23:12] Destination image height (For more information refer to chapter 15-3) DSTWidth [11:0] Destination image width (For more information refer to chapter 15-3)
Page 459 POST PROCESSOR S3C6400X RISC MICROPROCESSOR DMA Start Address Register for SW trigger Mode Register Address Description Reset Value DMA (Buffer 0) Start address for ADDRStart_Y 0x77000020 [30:0] 0x20000000 source Y or RGB component Register Address Description Reset Value DMA (Buffer 0) Start address for...
Page 460 S3C6400X RISC MICROPROCESSOR POST PROCESSOR DMA End Address Register for SW trigger Mode Register Address Description Reset Value DMA (Buffer 0) End address for ADDREnd_Y 0x77000030 [30:0] source Y or RGB component (For 0x20006300 more information refer to chapter 15-4)
Page 461 POST PROCESSOR S3C6400X RISC MICROPROCESSOR Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register Register Address Description Reset Value Offset of Y or RGB component for fetching Offset_Y 0x77000040 [23:0] source image (For more information refer to chapter 15-4) Register Address Description...
Page 462 S3C6400X RISC MICROPROCESSOR POST PROCESSOR Next Frame DMA Start Address Register for SW trigger Mode Register Address Description Reset Value Next Frame (Buffer 1) DMA Start NxtADDRStart_Y 0x77000054 [30:0] address for source Y or RGB 0x20000000 component Register Address Description...
Page 463 POST PROCESSOR S3C6400X RISC MICROPROCESSOR Next Frame DMA End Address Register for SW trigger Mode Register Address Description Reset Value Next Frame (Buffer 1) DMA End address for source Y or RGB NxtADDREnd_Y 0x77000064 [30:0] 0x20006300 component (For more information refer...
Page 464 S3C6400X RISC MICROPROCESSOR POST PROCESSOR DMA Start Address Register for Output Cb and Cr Register Address Description Reset Value DMA (Buffer 0) Start address for ADDRStart_oCb 0x77000074 [30:0] 0x20000000 destination Cb component Register Address Description Reset Value DMA (Buffer 0) Start address for...
Page 465 POST PROCESSOR S3C6400X RISC MICROPROCESSOR Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register for Output Cb and Cr Register Address Description Reset Value Offset of Cb component for fetching Offset_oCb 0x77000084 [23:0] destination image (For more information refer to chapter 15-4)
Page 466 S3C6400X RISC MICROPROCESSOR POST PROCESSOR Next Frame DMA End Address Register for Output Cb and Cr Register Address Description Reset Value Next Frame DMA (Buffer 1) End address for destination Cb component NxtADDREnd_oCb 0x77000094 [30:0] 0x20006300 (For more information refer to chapter...
Page 467 POST PROCESSOR S3C6400X RISC MICROPROCESSOR MODE Control Register 2 Register Address Description Reset Value MODE_2 0x770000A0 Mode Register 2 MODE_2 Description Initial State ADDR_CH_DIS Next Address Change Disable in Free Run Mode (Software Trigger Mode) When the current frame is completely finished and ADDR_CH_DIS is 0, Next frame address set of NxtADDRXXX is copied into the current frame address set of ADDRXXX.
Page 468 S3C6400X RISC MICROPROCESSOR TV SCALER TV SCALER (POST PROCESSOR VER2.5) This chapter describes the functions and usage of TV Scaler in S3C6400. OVERVIEW TV Scaler is similar to Post Processor except FIFO size (targeted SD TV) and Input FIFO Mode (Figure 16-2).
Page 469 TV SCALER S3C6400X RISC MICROPROCESSOR OVERALL FEATURES AMBA AHB v2.0 compatible interface Dedicated DMA with offset address 3 Channel scaling pipelines for video/graphic scaling up/down or zooming in/out Video input format: 420, 422 format Graphic input format: 16-bit (565format) or 24-bit...
Page 470 S3C6400X RISC MICROPROCESSOR TV SCALER 2. A Source and Destination Image Data Format On top of FIMV TV Scaler, there are two output modes such as DMA mode and FIFO mode as shown in the following Figure 16-2 In FIFO mode (if LCDPathEnable = 1, For more information refer to chapter 6. Register File List), destination image is transferred to the FIFO in display controller (or some other IP with FIFO interface) without additional memory bandwidth such as TV SCALER-to-Memory and Memory-to-Display Controller.
Page 471 TV SCALER S3C6400X RISC MICROPROCESSOR 2.1 DMA Mode Operation Various source and destination image formats can be selected according to the mode configuration as described in Table 16-1 a). Source image format is one of the following YCbCr420, YCbCr422, RGB16-bit (565format) and RGB 24-bit format.
Page 472 S3C6400X RISC MICROPROCESSOR TV SCALER Table 16-1 a). Mode configuration for video/graphic source format and the corresponding data format MODE[8] MODE[3] MODE[2] MODE[1] MODE[15][0] Description SRC420 InRGB INTER- InRGB InYCbCr Data Format Video/Graphic LEAVE Format Format Format in Fig16-3and 4 ×...
Page 473 TV SCALER S3C6400X RISC MICROPROCESSOR WORD WORD Y Cb Y Cr Video Data Cb Cb Cb Cb Cb Y Cr Y 1 Frame 1 Frame Cr Cr Cr Cr Pixel Pixel Memory Space Memory Space (a) Non-Interleaving (b) Interleaving Figure 16-3 Data format stored in external...
Page 474 S3C6400X RISC MICROPROCESSOR TV SCALER 2.2 FIFO Mode Operation Output data format is determined by MODE[18] as described in Table 16-1 b). The output data format is fixed to 30-bit data, 10-bit per each component RGB or YCbCr444. The other specific mode configuration signals mentioned in Table 16-1 b) are ignored if ExtFIFOIn or LCDPathEnable is set to “1”.
Page 475 TV SCALER S3C6400X RISC MICROPROCESSOR As explained in the previous section, SRC_Width and DST_Width satisfies the word boundary constraints such that the number of horizontal pixel can be represented by kn where n = 1,2,3, … and k = 1 / 2 / 8 for 24bppRGB / 16bppRGB / YCbCr420 image, respectively.
Page 476 S3C6400X RISC MICROPROCESSOR TV SCALER else if (SRC_Height >= 32 × DST_Height) { PreScale_V_Ratio = 32; V_Shift = 5; } else if (SRC_Height >= 16 × DST_Height) { PreScale_V_Ratio = 16; V_Shift = 4; } else if (SRC_Height >= 8 × DST_Height) { PreScale_V_Ratio = 8; V_Shift = 3; } else if (SRC_Height >= 4 ×...
Page 477 TV SCALER S3C6400X RISC MICROPROCESSOR 4. DMA operation of Source and Destination Image There are three address categories such as start address, end address and offset address for DMA operation. Each address category consists of three source address components of Y/Cb/Cr and three destination address component of RGB/oCb/oCr.
Page 478 S3C6400X RISC MICROPROCESSOR TV SCALER 4.1 Start address Start address of ADDRStart_Y/Cb/Cr/RGB/oCb/oCr points the first word address where the corresponding component of Y/Cb/Cr/RGB/oCb/oCr is read or written. Each one must be aligned with word boundary (i.e. ADDRStart_X[1:0] = 00). ADDRStart_Cb and ADDRStart_Cr are valid only for the YCbCr420 source image format.
Page 479 TV SCALER S3C6400X RISC MICROPROCESSOR Where, Offset_Y/Cb/Cr/RGB = Memory size for offset per a horizontal line = Number of pixel (or sample) in horizontal offset × ByteSize_Per_Pixel (or Sample) ByteSize_Per_Pixel = 1 for YCbCr420 2 for 16-bit RGB and YcbCr422...
Page 480 S3C6400X RISC MICROPROCESSOR TV SCALER Offset address is used for the following two situations. One is to fetch some parts of source image in order to zoom in/out as shown in Figure 16-7 (a). The other is to restore destination image for PIP (picture-in-picture) applications as shown in Figure 16-7 (b).
Page 481 TV SCALER S3C6400X RISC MICROPROCESSOR 5. Frame Management of TV Scaler 5.1 Per Frame Management Mode Per frame management of TV Scaler are controlled by two control register such as POSTENVID and POSTINT as shown in Figure 16-8. “POSTENVID” triggers the operation of TV SCALER. It is automatically de-asserted when all operations of the given frame are completed.
Page 482 S3C6400X RISC MICROPROCESSOR TV SCALER 6. Register File Lists Register Address Description Reset Value MODE 0x76300000 R/W Mode Register 0x00070B12 PreScale_Ratio 0x76300004 R/W Pre-Scale ratio for vertical and horizontal PreScaleImgSize 0x76300008 R/W Pre-Scaled image size SRCImgSize 0x7630000C R/W Source image size...
Page 483 TV SCALER S3C6400X RISC MICROPROCESSOR Offset_Cb 0x76300044 R/W Offset of Cb component for fetching source image Offset_Cr 0x76300048 R/W Offset of Cr component for fetching source image Offset_RGB 0x7630004C R/W Offset of Y or RGB component for restoring destination image...
Page 484 S3C6400X RISC MICROPROCESSOR TV SCALER ADDREnd_oCr 0x76300080 R/W DMA (Buffer 0) End address for destination Cr 0x20000000 component Offset_oCb 0x76300084 R/W Offset of Cb component for fetching destination image Offset_oCr 0x76300088 R/W Offset of Cr component for fetching destination image...
Page 485 TV SCALER S3C6400X RISC MICROPROCESSOR MODE Control Register Register Address Description Reset Value MODE 0x76300000 Mode Register [31:0] 0x00070B12 MODE Description Initial State ExtFIFOIn [31] In FIFO Mode Enable. 1 for FIFO mode and 0 for DMA mode CLKVALUP [30]...
Page 486 S3C6400X RISC MICROPROCESSOR TV SCALER AutoLoadEnable [14] AutoLoadEnalbe. 0 for Per Frame mode and 1 for Free Run mode LCDPathEnable [13] Out FIFO Mode Enable. 1 for FIFO mode and 0 for DMA mode Interlace [12] Output scan method selection register only when FIFO mode (LCDPathEnable =1).
Page 487 TV SCALER S3C6400X RISC MICROPROCESSOR Figure 16-10 Internal clock scheme Block Diagram Preliminary product information describe products that are in development, 16-20 for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 488 S3C6400X RISC MICROPROCESSOR TV SCALER Pre-Scale Ratio Register Register Address Description Reset Value PreScale_Ratio 0x76300004 Pre-Scale ratio for vertical and horizontal. PreScale_Ratio Description Initial State PreScale_V_Ratio [13:7] Pre-scale ratio for vertical direction (For more information refer to chapter 16-3) PreScale_H_Ratio...
Page 489 TV SCALER S3C6400X RISC MICROPROCESSOR Source Image Size Register Register Address Description Reset Value SRCImgSize 0x7630000C Source image size SRCImgSize Description Initial State SRCHeight [23:12] Source image height (For more information refer to chapter 16-3) SRCWidth [11:0] Source image width (For more information refer to chapter 16-3)
Page 490 S3C6400X RISC MICROPROCESSOR TV SCALER Destination Image Size Register Register Address Description Reset Value DSTImgSize 0x76300018 Destination image size SRCImgSize Description Initial State DSTHeight [23:12] Destination image height (For more information refer to chapter 16- DSTWidth [11:0] Destination image width (For more information refer to chapter 16-...
Page 491 TV SCALER S3C6400X RISC MICROPROCESSOR DMA Start Address Register for SW trigger Mode Register Address Description Reset Value DMA (Buffer 0) Start address for ADDRStart_Y 0x76300020 [30:0] 0x20000000 source Y or RGB component Register Address Description Reset Value DMA (Buffer 0) Start address for...
Page 492 S3C6400X RISC MICROPROCESSOR TV SCALER DMA End Address Register for SW trigger Mode Register Address Description Reset Value DMA (Buffer 0) End address for ADDREnd_Y 0x76300030 [30:0] source Y or RGB component (For 0x20006300 more information refer to chapter 16-4)
Page 493 TV SCALER S3C6400X RISC MICROPROCESSOR Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register Register Address Description Reset Value Offset of Y or RGB component for fetching Offset_Y 0x76300040 [23:0] source image (For more information refer to chapter 16-4) Register Address Description...
Page 494 S3C6400X RISC MICROPROCESSOR TV SCALER Next Frame DMA Start Address Register for SW trigger Mode Register Address Description Reset Value Next Frame (Buffer 1) DMA Start NxtADDRStart_Y 0x76300054 [30:0] address for source Y or RGB 0x20000000 component Register Address Description...
Page 495 TV SCALER S3C6400X RISC MICROPROCESSOR Next Frame DMA End Address Register for SW trigger Mode Register Address Description Reset Value Next Frame (Buffer 1) DMA End address for source Y or RGB NxtADDREnd_Y 0x76300064 [30:0] 0x20006300 component (For more information refer...
Page 496 S3C6400X RISC MICROPROCESSOR TV SCALER DMA Start Address Register for Output Cb and Cr Register Address Description Reset Value DMA (Buffer 0) Start address for ADDRStart_oCb 0x76300074 [30:0] 0x20000000 destination Cb component Register Address Description Reset Value DMA (Buffer 0) Start address for...
Page 497 TV SCALER S3C6400X RISC MICROPROCESSOR Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register for Output Cb and Cr Register Address Description Reset Value Offset of Cb component for fetching Offset_oCb 0x76300084 [23:0] destination image (For more information refer to chapter 16-4)
Page 498 S3C6400X RISC MICROPROCESSOR TV SCALER Next Frame DMA End Address Register for Output Cb and Cr Register Address Description Reset Value Next Frame DMA (Buffer 1) End address for destination Cb component NxtADDREnd_oCb 0x76300094 [30:0] 0x20006300 (For more information refer to chapter...
Page 499 TV SCALER S3C6400X RISC MICROPROCESSOR MODE Control Register 2 Register Address Description Reset Value MODE_2 0x763000A0 Mode Register 2 MODE_2 Description Initial State FIFO_OUT_PA [6:5] FIFO output path selection 00 = TV Encoder output 01 = FIMD WIN1 1x = FIMD WIN2...
Page 500 S3C6400X RISC MICROPROCESSOR TV ENCODER TV ENCODER OVERVIEW This is TV Encoder which coverts digital video data to analog composite. TV Encoder in S3C6400 has a few special features. First of all, it has the image enhancing engine. The image is enhanced by special effects.
Page 501 TV ENCODER S3C6400X RISC MICROPROCESSOR BLOCK DIAGRAM Macrovision Sync Y(CVBS) SFR Control Block Control Signal Timing Generator Control Signal Image Enhancer Scaler FIFO Carrier (2048 depth) Data Signal Data Signal TV Controller Enhancing & Encoding Block Figure 17-1. TV Encoder Block Diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 502 S3C6400X RISC MICROPROCESSOR TV ENCODER FUNCTIONAL DESCRIPTIONS TV Encoder encodes digital pixel data to ITU-R BT.656 format. TV Encoder largely consists of 4 parts. The first part is the Enhancer & Encoder block. The Enhancer & Encoder block contains the encoder and the image enhancer.
Page 503 TV ENCODER S3C6400X RISC MICROPROCESSOR COMPOSITION OF ANALOG COMPOSITE SIGNAL White Level 100 IRE Data Black Level 7.5 IRE Blank Level 40 IRE Sync Level Back Porch Active Front Porch 13.5MHz (1 Field) Figure 17-3. Composition of Analog Composite Signal Figure 17-3 shows horizontal timing.
Page 504 S3C6400X RISC MICROPROCESSOR TV ENCODER COMMON NTSC SYSTEM "M" "NTSC-J" "NTSC 4.43" LINE/FIELD = 525 / 59.94 LINE/FIELD = 525 / 59.94 LINE/FIELD = 525 / 59.94 FH = 15.734 KHZ FH = 15.734 KHZ FH = 15.734 KHZ FV = 59.94 HZ FV = 59.94 HZ...
Page 505 TV ENCODER S3C6400X RISC MICROPROCESSOR COMMON PAL SYSTEM "I" "B, B1, G, H" "M" LINE/FIELD = 625 / 50 LINE/FIELD = 625 / 50 LINE/FIELD = 525 / 59.94 FH = 15.625 KHZ FH = 15.625 KHZ FH = 15.734 KHZ...
Page 506 S3C6400X RISC MICROPROCESSOR TV ENCODER COMPOSITION OF SCREEN 858(60Hz) or 864(50Hz) 1716(60Hz) or 1728(50Hz) Vertical Sync region Back-porch under-scan 1440(720), 60Hz or 50Hz region Active region Vertical Front-porch Horizontal Horizontal Back-porch Front-porch Figure 17-6. Composition of TV screen In 60Hz type, The size of a frame is 858x525. This contains synchronous and real image region. Real image is 720x480.
Page 507 TV ENCODER S3C6400X RISC MICROPROCESSOR REQUESTED HORIZONTAL TIMING Figure 17-7. Requested Horizontal Timing Diagram Figure 17-7 shows us the horizontal timing relation. The horizontal line is composed of active and synchronous region. In 60Hz, a line consists of active 1440 pixel, front porch 32 pixel and back porch (containing synch width) 244 pixel.
Page 508 S3C6400X RISC MICROPROCESSOR TV ENCODER REQUESTED VERTICAL TIMING Figure 17-8. Requested Vertical Timing Diagram in 60Hz Figure 17-9. Requested Vertical Timing Diagram in 50Hz Preliminary product information describe products that are in development, 17-9 for which full characterization data and associated errata are not yet available.
Page 509 TV ENCODER S3C6400X RISC MICROPROCESSOR EXPLAINATION OF IMAGE ENHANCER TERMNINOLOGY White Tilt Point Black Tilt Point OUTPUT IMAGE ENERGY Figure 17-10. The concept of Tilt Point in White and Black Stretch Tilt point means the inflection point in in/out energy equation. The equation is usually linear. But if we makes inflection points in the equation, we can get another resolution in in-out relation.
Page 510 S3C6400X RISC MICROPROCESSOR TV ENCODER MACROVISION The macrovision is the anti-taping standard that is suggested by Macrovision Corporation. The macrovision has the following features: — Pseudo sync, AGC pulses generation — End of field back porch pulse — Color-stripe — Timing cycle...
Page 511 TV ENCODER S3C6400X RISC MICROPROCESSOR For burst For burst start& parameters H-sync duration (except burst start) Start of burst to 2'nd phase 1'st to 2'nd phase 1'st phase switch point to switch point Colorsrtipe line switch point end of burst...
Page 512 S3C6400X RISC MICROPROCESSOR TV ENCODER N10 [7:4] : The number of EOF pulse(0~15ea) after Vsync de-asserts N10 [3:0] : The number of EOF N12 [0:14] : AGC pulse type A / B (7~21 line) pulse(0~15ea) before Vsync asserts N11 [0:14] : P.S and AGC on/off...
Page 513 TV ENCODER S3C6400X RISC MICROPROCESSOR REGISTER INITIAL VALUE EXAMPLE Table 17-1 Example of Macrovision initial value NTSC PATTERN REGISTER VALUE PATTERN REGISTER VALUE Macrovision0 0x2115D73E Macrovision0 0x25111D3E Macrovision1 0x02050515 Macrovision1 0x00070101 Macrovision2 0x00241B1B Macrovision2 0x00241B1B AGC 4L AGC 2L Macrovision3...
Page 514 S3C6400X RISC MICROPROCESSOR TV ENCODER DAC BOARD CONFIGURE GUIDE Zo = 75 6.6[mA] =75[ohm] = 150[ohm] Figure 17-13. DAC Board Guide It is the current drive DAC in S3C6400. Output current is 6.6mA. So, it has to load 150[ohm] resistor. And it is recommended to use AMP equipment.
Page 515 TV ENCODER S3C6400X RISC MICROPROCESSOR TV ENCODER REGISTER SUMMARY Register Address Description Reset Value TVCTRL 0x76200000 TV Controller control SFR set 0x00010000 VBPORCH 0x76200004 Vertical back porch end point 0x011C0015 HBPORCH 0x76200008 Horizontal back porch end point 0x008000F4 HEnhOffset 0x7620000C...
Page 516 S3C6400X RISC MICROPROCESSOR TV ENCODER INDIVIDUAL REGISTER DESCRIPTIONS TVENCREG1 Register Address Description Reset Value TVCTRL 0x76200000 TV Controller control SFR set 0x00010000 TVCTRL Description Reset Value [31:17] Reserved FIFO under-run interrupt control INTFIFOUR [16] 0 : Disable 1 : Enable...
Page 517 TV ENCODER S3C6400X RISC MICROPROCESSOR TVENCREG2 Register Address Description Reset Value VBPORCH 0x76200004 Vertical back porch end point 0x011C0015 VBPORCH Description Reset Value [31:25] Reserved Vertical even field back porch end point VEFBPD [24:16] 0x11C NTSC : 0x11C(284) , PAL : 0x14F(335)
Page 518 S3C6400X RISC MICROPROCESSOR TV ENCODER TVENCREG5 Register Address Description Reset Value VDemoWinSize 0x76200010 Vertical demo window size 0x00F00000 VDemoWinSize Description Reset Value [31:25] Reserved Vertical demo window size VDWS [24:16] 0xF0 Default : 0xF0(240) [15:9] Reserved Vertical demo window start point...
Page 519 TV ENCODER S3C6400X RISC MICROPROCESSOR ENCODER TVENCREG8 Register Address Description Reset Value PEDCTRL 0x7620001C Encoder pedestal control 0x00000000 PEDCTRL Description Reset Value [31:1] Reserved Encoder pedestal control PEDOff 0 : Pedestal on(NTSCM & PALM) 1 : Pedestal off(Even NTSCM & PALM)
Page 520 S3C6400X RISC MICROPROCESSOR TV ENCODER TVENCREG10 Register Address Description Reset Value HUECTRL 0x76200024 HUE control 0x00000000 HUECTRL Description Reset Value [31:8] Reserved Color HUE control(with an increment of 1.4063’) 0x00 : 0’ phase shift … [7:0] 0x80 : 180’ phase shift …...
Page 521 TV ENCODER S3C6400X RISC MICROPROCESSOR TVENCREG14 Register Address Description Reset Value BGCTRL 0x76200034 Background control 0x00000110 BGCTRL Description Reset Value [31:9] Reserved Soft mixed enable 0 : Disable 1 : Enable soft mixed for background border Reserved Background color select...
Page 522 S3C6400X RISC MICROPROCESSOR TV ENCODER Figure 17-14. The Calculation Method of Back-ground Preliminary product information describe products that are in development, 17-23 for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 523 TV ENCODER S3C6400X RISC MICROPROCESSOR IMAGE ENHANCER TVENCREG18 Register Address Description Reset Value ContraBright 0x76200044 Contrast & Bright control 0x00000040 ContraBright Description Reset Value [31:24] Reserved Brightness control(2’s) BRIGHT [23:16] 0x7F : Maximum brightness 0x00 0x80 : Minimum brightness [15:8]...
Page 524 S3C6400X RISC MICROPROCESSOR TV ENCODER TVENCREG20 Register Address Description Reset Value DemoWinCTRL 0x7620004C Demo window control 0x00000010 DemoWinCTRL Description Reset Value [31:25] Reserved Enhancer demo window on/off MVDemo [24] 0 : Normal operation 1 : Enhancer demonstration window mode [23:17]...
Page 525 TV ENCODER S3C6400X RISC MICROPROCESSOR TVENCREG21 Register Address Description Reset Value FTCA 0x76200050 Flesh tone control 0x00D7008C FTCA Description Reset Value [31:24] Reserved Flesh tone correction angle : Cosine value <Equation> FTCAC [23:16] FTCAC = cos( x – 90’) * (2^8) ( x : 90 ~ 180 degree )
Page 526 S3C6400X RISC MICROPROCESSOR TV ENCODER TVENCREG25 Register Address Description Reset Value SharpCTRL 0x76200060 Sharpness control 0x0304501F SharpCTRL Description Reset Value [31:28] Reserved SHARPT [27:20] Dynamic sharpness tilt point 0x30 [19:15] Reserved Sharpness coring control SDhCor [14:12] 0 : Disable coring...
Page 527 TV ENCODER S3C6400X RISC MICROPROCESSOR TVENCREG26 Register Address Description Reset Value GammaCTRL 0x76200064 Gamma control 0x00000104 GammaCTRL Description Reset Value [31:13] Reserved Gamma enable GamEn [12] 0 : Gamma disable 1 : Gamma enable [11:10] Reserved Gamma control mode GamMode...
Page 528 S3C6400X RISC MICROPROCESSOR TV ENCODER TVENCREG28 Register Address Description Reset Value SyncSizeCTRL 0x7620006C Sync size control 0x0000003D SyncSizeCTRL Description Reset Value [31:10] Reserved Hsync size SySize [9:0] 0x3D : NTSC 0x3D 0x3E : PAL TVENCREG29 Register Address Description Reset Value...
Page 529 TV ENCODER S3C6400X RISC MICROPROCESSOR TVENCREG31 Register Address Description Reset Value ActVidPoCTRL 0x76200078 Active video position control 0x03480078 ActVidPoCTRL Description Reset Value [31:26] Reserved Active video end position AvonEnd [25:16] 0x348 : NTSC 0x348 0x352 : PAL [15:10] Reserved Active video start position...
Page 530 S3C6400X RISC MICROPROCESSOR TV ENCODER TVENCREG34 Register Address Description Reset Value Macrovision0 0x76200084 Macrovision control 0 0x21151700 Macrovision0 Description Reset Value [31:30] Reserved [29:24] Macrovision control N3 0x21 [23:22] Reserved [21:16] Macrovision control N2 0x15 [15:14] Reserved [13:8] Macrovision control N1...
Page 531 TV ENCODER S3C6400X RISC MICROPROCESSOR TVENCREG37 Register Address Description Reset Value Macrovision3 0x76200090 Macrovision control 3 0x000007F8 Macrovision3 Description Reset Value [31] Reserved [30:16] Macrovision control N12 [15] Reserved [14:0] Macrovision control N11 0x07F8 TVENCREG38 Register Address Description Reset Value...
Page 532 S3C6400X RISC MICROPROCESSOR TV ENCODER TVENCREG40 Register Address Description Reset Value Macrovision6 0x7620009C Macrovision control 6 0x000003FF Macrovision6 Description Reset Value [31:10] Reserved [9:0] Macrovision control N21 0x3FF Preliminary product information describe products that are in development, 17-33 for which full characterization data and associated errata are not yet available.
Page 533 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D GRAPHICS 2D OVERVIEW FIMG-2D is a 2D graphics accelerator that supports three types of primitive drawings: Line/Point Drawing, Bit Block Transfer (BitBLT) and Color Expansion (Text Drawing). Rendering a primitive takes two steps: 1) configure the rendering parameters, such as foreground color and the coordinate data, by setting the drawing-context registers;...
Page 534: Data Format
GRAPHICS 2D S3C6400X RISC MICROPROCESSOR FEATURES ♦ Primitives Line/Point Drawing DDA ( Digital Differential Analyzer) algorithm Do-Not-Draw Last Point support BitBLT Stretched BitBLT support ( Nearest sample ) Screen to Screen Host to Screen Color Expansion Memory to Screen Host to Screen ♦...
Page 535 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D COLOR FORMAT FIMG2D supports the following color format: 15/16/18/24/32-bit per pixel. Each format is illustrated as below: 15-bpp 1 bit R (5 bits) G (5 bits) B (5 bits) 16-bpp R (5 bits) G (6 bits)
Page 536 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR COORD_0 Coordinate of the starting point COORD_2 Coordinate of the ending point ( ignored if a point is rendered ) X-INCR X increment value ( ignored if x-axis is the Major Axis or a point is rendered)
Page 537 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D CMDR_1 is disabled or host-to-screen mode is used. Y increment value of the source image coordinates. If it is greater than 1, the image Y-INCR is shrunk vertically; smaller than 1, stretched. This value is ignored when S bit in CMDR_1 is disabled or host-to-screen mode is used.
Page 538 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR COORD_0 Coordinate of the leftmost topmost coordinate of the destination window COORD_1 Coordinate of the rightmost bottommost coordinate of the destination window FG_COLOR Foreground Color BG_COLOR Background Color The base address of the font data. Note that writing to this register starts the CMDR_7 rendering process in the memory-to-screen mode.
Page 539 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D 4) Final Data = Source AND Destination. ROP Value = “11110000” & “11001100” = “11000000” 5) Final Data = Source OR Pattern. ROP Value = “11110000” | “10101010” = “11111010”. Related Registers PATTERN_REG[0:31] Pattern data...
Page 540 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR ROTATION The pixels can be rotated around the reference point (ox, oy) by 90/180/270 degree clockwise or perform a X- axis/Y-axis flip around the horizontal or vertical line on which (ox, oy) lies. The effects of all rotation options are summarized in the following table and illustrated in Figure 3.
Page 541 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D CLIPPING Clipping discards the pixels (after rotation) outside the clipping window. The color data of the discarded pixels will not be written into the framebuffer. Related Registers CW_LT_REG Coordinate of the leftmost topmost point of the clipping window...
Page 542 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR REGISTER DESCRIPTIONS MEMORY MAP Register Offset Description Reset Value General Registers INTEN_REG 0x76100004 R/W Interrupt Enable register. 0x0000_0000 FIFO_INTC_REG 0x76100008 R/W Interrupt Control register 0x0000_0018 INTC_PEND_REG 0x7610000C R/W Interrupt Control Pending register. 0x0000_0000 FIFO_STAT_REG 0x76100010 Command FIFO Status register.
Page 543 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D COORD0_Y_REG 0x76100308 Y coordinate of Coordinates 0. 0x0000_0000- COORD1_REG 0x76100310 R/W Coordinates 1 register. 0x0000_0000 COORD1_X_REG 0x76100314 X coordinate of Coordinates 1. 0x0000_0000- COORD1_Y_REG 0x76100318 Y coordinate of Coordinates 1. 0x0000_0000- COORD2_REG 0x76100320 R/W Coordinates 2 register.
Page 544 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR INDIVIDUAL REGISTER DESCRIPTION GENERAL INTERRUPT ENABLE REGISTER (INTEN_REG) Register Offset Description Reset Value INTEN_REG 0x76100004 Interrupt Enable register. 0x0000_0000 INTEN_REG Description Initial State Reserved [31:10] [10] Drawing Engine Finished Interrupt Enable. All command Finished Interrupt Enable. When all commands are executed (no command in the Command FIFO), this bit will be set.
Page 545 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D INTC_PEND_REG Description CLRSEL [31] Level interrupt & pulse interrupt mode select. 1 : level interrupt mode select(interrupt clear enable) 0: pulse interrupt mode select Reserved [30:11] INTP_DE_FIN [10] Graphics Drawing Engine finished. INTP_FINISH_ALL Graphics Engine IDLE state.
Page 546 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR COMMAND LINE DRAWING REGISTER (CMD0_REG) Register Offset Description Reset Value CMD0_REG 0x76100100 Command register for Line/Point drawing. CMD0_REG Description Initial State Reserved [31:10] 0 : Draw Last Point 1 : Do-not-Draw Last Point. 0 : Major axis is Y.
Page 547 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D COMMAND HOST TO SCREEN CONTINUE BITBLT REGISTER (CMD3_REG) Register Offset Description Reset Value Command register for Host to Screen Bitblt CMD3_REG 0x7610010C transfer continue. CMD3_REG Description Initial State Data [31:0] BitBLT continuous data. COMMAND HOST TO SCREEN START COLOR EXPANSION REGISTER (CMD4_REG)
Page 548 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR COMMON RESOURCE COLOR MODE (COLOR_MODE_REG) Register Offset Description Reset Value COLOR_MODE_REG 0x76100200 Color Mode register. 0x0000_0008 COLOR_MODE_REG Description Initial State Reserved [31:4] 24/32-bpp 18-bpp 16-bpp 15-bpp COMMON RESOURCE HORIZONTAL RESOLUTION (HORI_RES_REG) Register Offset Description Reset Value...
Page 549 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D COMMON RESOURCE SCREEN CLIPPING MAX_X WINDOW (SC_WIN_X_REG) Register Offset Description Reset Value SC_WIN_X_REG 0x76100214 Max.X of Screen Clip Window register. 0x0000_0000 SC_WIN_X_REG Description Initial State Reserved [31:11] MaxSX [10:0] Max Screen Clipping X Window COMMON RESOURCE SCREEN CLIPPING MAX_Y WINDOW (SC_WIN_Y_REG)
Page 550 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR COMMON RESOURCE TOP Y CLIPPING WINDOW (CW_LT_Y_REG) Register Offset Description Reset Value CW_LT_Y_REG 0x76100228 Top Y coordinate of Clip Window. 0x0000_0000 CW_LT_Y_REG Description Initial State Reserved [31:11] TopCW_Y [10:0] Top Y Clipping Window COMMON RESOURCE RIGHTBOTTOM CLIPPING WINDOW (CW_RB_REG)
Page 551 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D COMMON RESOURCE COORDINATE_0 REGISTER (COORD0_REG) Register Offset Description Reset Value COORD0_REG 0x76100300 Coordinates 0 register. 0x0000_0000 COORD0_REG Description Initial State Reserved [31:27] [26:16] Coordinate_0 Y Reserved [15:11] [10:0] Coordinate_0 X COMMON RESOURCE COORDINATE_0 X REGISTER (COORD0_X_REG)
Page 552 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR COORD1_REG Description Initial State Reserved [31:27] [26:16] Coordinate_1 Y Reserved [15:11] [10:0] Coordinate_1 X COMMON RESOURCE COORDINATE_1 X REGISTER (COORD1_X_REG) Register Offset Description Reset Value COORD1_X_REG 0x76100314 X coordinate of Coordinates 1. 0x0000_0000 COORD1_X_REG Description...
Page 553 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D COMMON RESOURCE COORDINATE_2 X REGISTER (COORD2_X_REG) Register Offset Description Reset Value COORD2_X_REG 0x76100324 X coordinate of Coordinates 2. 0x0000_0000 COORD2_X_REG Description Initial State Reserved [31:11] COORD2_X [10:0] Coordinate_2 X COMMON RESOURCE COORDINATE_2 Y REGISTER (COORD2_Y_REG)
Page 554 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR COMMON RESOURCE COORDINATE_3 X REGISTER (COORD3_X_REG) Register Offset Description Reset Value COORD3_X_REG 0x76100334 X coordinate of Coordinates 3. 0x0000_0000 COORD3_X_REG Description Initial State Reserved [31:11] COORD3_X [10:0] Coordinate_3 X COMMON RESOURCE COORDINATE_3 Y REGISTER (COORD3_Y_REG)
Page 555 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D COMMON RESOURCE ROTATION ORIGIN COORDINATE Y (ROT_OC_Y_REG) Register Offset Description Reset Value ROT_OC_Y_REG 0x76100348 Y coordinate of Rotation Origin Coordinates. 0x0000_0000 ROT_OC_Y_REG Description Initial State Reserved [31:1] ROT_OC_Y [10:0] Rotation Origin Coordinate Y COMMON RESOURCE ROTATION REGISTER (ROTATE_REG)
Page 556 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR COMMON RESOURCE READ SIZE (ENDIAN_READSIZE) Register Offset Description Reset Value ENDIA_READSIZE 0x76100350 Read size select 0x0000_0001 ENDIA_READSIZE Description Initial State Reserved [31:5] Reserved Should be ‘0’ Reserved SIZE_HW 1’b0 : h/w setting read buffer size disable.
Page 557 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D COMMON RESOURCE RASTER OPERATION REGISTER (ROP_REG) Register Offset Description Reset Value ROP_REG 0x76100410 Raster Operation register. 0x0000_0000 ROP_REG Description Initial State Reserved [31:14] [13] Third Operand Select : 1’b0 : Pattern 1’b1 : Foreground Color...
Page 558 GRAPHICS 2D S3C6400X RISC MICROPROCESSOR COMMON RESOURCE FOREGROUND COLOR REGISTER (FG_COLOR_REG) Register Offset Description Reset Value FG_COLOR_REG 0x76100500 Foreground Color / Alpha register. 0x0000_0000 FG_COLOR_REG Description Initial State Reserved [31:24] ForegroundColor [23:0] Foreground Color Value COMMON RESOURCE BACKGROUND COLOR REGISTER (BG_COLOR_REG)
Page 559 S3C6400X RISC MICROPROCESSOR GRAPHICS 2D COMMON RESOURCE PATTERN OFFSET REGISTER (PATOFF_REG) Register Offset Description Reset Value PATOFF_REG 0x76100700 Pattern Offset XY register. 0x0000_0000 PATOFF_REG Description Initial State Reserved [31:19] POffsetY [18:16] Pattern Offset Y Value Reserved [15:3] POffsetX [2:0] Pattern OffsetX Value...
Page 560 S3C6400 RISC MICROPROCESSOR IMAGE ROTATOR IMAGE ROTATOR OVERVIEW Image Rotator performs rotating/flipping image data. It is composed of Rotate FSM, Rotate Buffer, AMBA AHB 2.0 master/slave interface, and Register files. Overall features are summarized as follows. FEATURE Supports image format: YCbCr 4:2:2(interleave), YCbCr 4:2:0(non-interleave), RGB565 and RGB888(unpacked) Supports rotate degree: 90, 180, 270, flip vertical and flip horizontal BLOCK DIAGRAM...
Page 561 IMAGE ROTATOR S3C6400 RISC MICROPROCESSOR ORIGINAL IMAGE FLIP VERTICAL FLIP HORIZONTAL 180-DEGREE ROTATION Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 19-2 Specifications and information herein are subject to change without notice.
Page 562 S3C6400 RISC MICROPROCESSOR IMAGE ROTATOR 90 AND 270-DEGREE ROTATION Preliminary product information describe products that are in development, 19-3 for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 563 IMAGE ROTATOR S3C6400 RISC MICROPROCESSOR REGISTER DESCRIPTION MEMORY MAP Register Address Description Reset Value CTRLCFG 0x7720_0000 Rotator Control Register 0x000_0000 SRCADDRREG0 0x7720_0004 Rotator Source Image (RGB or Y component) 0x0000_0000 Address Register SRCADDRREG1 0x7720_0008 Rotator Source Image (CB component) 0x0000_0000 Address Register SRCADDRREG2 0x7720_000C...
Page 564 S3C6400 RISC MICROPROCESSOR IMAGE ROTATOR ROTATOR SOURCE IMAGE ADDRESS REGISTER 0 (RGB OR Y COMPONENT) Register Address Description Reset Value SRCADDRREG0 0x7720_0004 Rotator Source Image Address Register 0x0000_0000 SRCADDRREG0 Description Initial State Source Address [30:0] The address of source image. 0x0000_0000 ROTATOR SOURCE IMAGE ADDRESS REGISTER 1 (CB COMPONENT) Register...
Page 565 IMAGE ROTATOR S3C6400 RISC MICROPROCESSOR DESTADDRREG1 0x7720_001C Rotator Destination Image Address Register 0x0000_0000 DESTADDRREG Description Initial State [30:0] The address of destination image. 0x0000_0000 Destination Address ROTATOR DESTINATION IMAGE ADDRESS REGISTER 2 (CR COMPONENT) Register Address Description Reset Value DESTADDRREG2 0x7720_0020 Rotator Destination Image Address Register 0x0000_0000...
Page 566: Camera Interface
Two Output DMAs exist. The one is the Preview DMA. The other one is the Codec DMA. Two DMA are dedicated to the YCbCr 4:2:2, YCbCr 4:2:0 and RGB output. The CAMERA INTERFACE in S3C6400X has image rotator (90’ clockwise) and image effect. These features are very useful in folder type cellular phone.
Page 567 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR Camera interface YCbCr 4:2:2 T_patternMux CatchCam ITU-R BT 601/656 Memory Memory MSDMA MSDMA YCbCr 4:2:0 YCbCr 4:2:0 YCbCr 4:2:2 YCbCr 4:2:2 Codec Scaler Preview Scaler YCbCr / RGB YCbCr / RGB Pre-Scaler Pre-Scaler Main-Scaler Main-Scaler...
Page 568 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE EXTERNAL INTERFACE Camera Interface can support the next video standards. Two video standards are as follows: — ITU-R BT 601 YCbCr 8-bit mode — ITU-R BT 656 YCbCr 8-bit mode SIGNAL DESCRIPTION Name Description External camera processor interface signal...
Page 569 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR TIMING DIAGRAM 1 frame VSYNC Vertical lines HREF HREF (1H) Horizontal width PCLK 8- bit mode DATA[7:0] Figure 20-2. ITU-R BT 601 Input timing diagram PCLK DATA[7:0] Video timing Video timing reference codes reference codes Pixel data Figure 20-3.
Page 570 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Table 20-3. Video timing reference codes of ITU-656 8bit format Note: F = 0 (during field 1), 1 (during field 2) V = 0 (elsewhere), 1 (during field blanking) H = 0 (in SAV : Start of Active Video), 1 (in EAV : End of Active Video)
Page 571 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR Note: If rotator is enabled, (t4 + t1) must be long enough to finish DMA transactions. It is because, DMA transaction for rotator line buffer are delayed by 4 or 8 horizontal lines. EXTERNAL/INTERNAL CONNECTION GUIDE All Camera Interface input signals must not occur inter-skewing to pixel clock line.
Page 572 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE CAMERA INTERFACE OPERATION FOUR DMA PORTS Camera Interface has Four DMA port. MSDMA input for preview, MSDMA input for codec, P-port(Preview out port) and C-port(Codec out port) are separated from each other on AHB bus. At the view of system bus, four ports are independent.
Page 573 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR CLOCK DOMAIN Camera Interface has two clock domains. The one is the system bus clock, which is HCLK. The other is the pixel clock, which is PCLK. The system clock must be faster than pixel clock. As highlighted in figure 20- 7, CAMCLK must be divided from the fixed frequency like APLL or MPLL clock.
Page 574 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE FRAME MEMORY HIERARCHY Frame memories consist of four ping-pong memories for each P-ports and C-ports. Ping-pong memories have three element memories that are luminance Y, chrominance Cb, and chrominance Cr. It is recommended that the arbitration priority of CAMERA INTERFACE must be higher than any other masters except LCD controller.
Page 575 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR MEMORY STORING METHOD The little-endian method is the storing method to the frame memory. The first entering pixels stored into LSB sides, and the last entering pixels stored into MSB sides. The carried data by AHB bus is 32-bit word. Therefore, CAMERA INTERFACE make the each Y-Cb-Cr words by little endian style.
Page 576 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Little endian method Y frame memory ITU-601/656 YCbCr Little endian method 4:2:2 8-bit input timing Cb frame memory PCLK Camera Interface time Little endian method Cr frame memory 32-bit C4 C3 C2 C1 Little endian method...
Page 577 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR TIMING DIAGRAM FOR REGISTER SETTING The first register setting for frame capture command can occur in any part of frame period. It is recommend to do first setting at the VSYNC “L” state. VSYNC information can be read from status SFR. Refer to the below figure 20-10.
Page 578 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Read Memory SFR setting (ENVID_M_P or ENVID_M_C) Image Capture SFR setting (ImgCptEn_PrSc or ImgCptEn_CoSC) SEL_DMA_CAM SFR setting (SEL_DMA_CAM) < Frame Capture Start for MSDMA input > MSDMA end P or C-Port DMA end Read Memory...
Page 579 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR TIMING DIAGRAM FOR LAST IRQ (CAMERA CAPTURE MODE) IRQ except LastIRQ is generated before image capturing. Last IRQ which means camera signal capture-end can be set by following timing diagram. LastIRQEn is auto-cleared and, as mentioned, SFR setting in ISR is for next frame command.
Page 580 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM FOR IRQ (MEMORY DATA SCALING MODE) - MSDMA input can be selected by SFR setting. In this case, IRQ is generated after P-port or C-port DMA operation completed for per frame. This mode is aware of starting point by user’s SFR setting (ENVID ‘0’ → ‘1’).
Page 581: Software Interface
MSDMA path Figure 20-15. MSDMA or External Camera interface SOFTWARE INTERFACE ( CAMERA INTERFACE IN S3C6400X SFR) CAMERA INTERFACE SPECIAL FUNCTION REGISTERS ※ The last ‘L’ column means that SFR can change at vsync edge during camera capturing. (O : possible change, X : impossible change).
Page 582 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Initial CISRCFMT Description State 1 : ITU-R BT.601 YCbCr 8-bit mode enable ITU601_656n [31] 0 : ITU-R BT.656 YCbCr 8-bit mode enable Cb,Cr value offset control. UVOffset [30] 1 : +128 0 : +0 (normally used)
Page 583 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR ( WinHorOfst2 & WinVerOfst2 are assigned in the CIWDOFST2 register ) Initial CIWDOFST Description State 1 : window offset enable WinOfsEn [31] 0 : no offset 1 : clear the overflow indication flag of input CODEC FIFO Y...
Page 584 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE GLOBAL CONTROL REGISTER Register Address Description Reset Value CIGCTRL 0x78000008 Global control register 2000_0000 Initial CIGCTRL Description State Camera interface software reset. Before setting this bit, you must set the ITU601_656n bit of CISRCFMT as “1” temporarily at first SFR setting.
Page 585 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR O v e r f lo w ( p r e v ie w ) IR Q _ C l_ p IR Q _ p IR Q _ O v f e n O v e r f lo w...
Page 586 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE CODEC OUTPUT Y1 START ADDRESS REGISTER Register Address Description Reset Value CICOYSA1 0x78000018 frame start address for codec DMA Initial CICOYSA1 Description State CICOYSA1 [31:0] Non-Interleave Y, Interleave YCbCr, RGB : 1 frame start address...
Page 587 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR CODEC OUTPUT CB1 START ADDRESS REGISTER Register Address Description Reset Value CICOCBSA1 0x78000028 Cb 1 frame start address for codec DMA Initial CICOCBSA1 Description State CICOCBSA1 [31:0] Cb 1 frame start address for codec DMA...
Page 588 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE CODEC OUTPUT CR1 START ADDRESS REGISTER Register Address Description Reset Value CICOCRSA1 0x78000038 Cr 1 frame start address for codec DMA Initial CICOCRSA1 Description State CICOCRSA1 [31:0] Cr 1 frame start address for codec DMA...
Page 589 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR CODEC TARGET FORMAT REGISTER Register Address Description Reset Value CICOTRGFMT 0x78000048 Target image format of codec DMA Figure 20-18. Codec image mirror Initial CICOTRGFMT Description State Reserved [31] 00 : YCbCr 4:2:0 codec output image format. (Non-interleave) 01 : YCbCr 4:2:2 codec output image format.
Page 590 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE CODEC DMA CONTROL REGISTER Register Address Description Reset Value CICOCTRL 0x7800004C Codec DMA control related Initial CICOCTRL Description State Reserved [31:24] Yburst1_Co [23:19] Main burst length for codec Y frames Yburst2_Co [18:14] Remained burst length for codec Y frames...
Page 591 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR ※ Non-Interleaved burst length (Y burst length – YcbCr 4:2:0, YCbCr 4:2:2) Main burst length = 4, 8, 16 Remained burst length = 4, 8, 16 Main burst length = 2, 4, 8, 16 Remained burst length = 2, 4, 8, 16 ※...
Page 592 2, and at crossing 1024 address boundary by single transfer. System controller including CAMERA INTERFACE in S3C6400X must support to treat INCR burst as several single transfer accesses. Watch over your memory controller and system arbiter specification!
Page 593 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR If ( SRC_Width >= 64 × DST_Width ) { Exit(-1); /* Out Of Horizontal Scale Range */ } else if (SRC_Width >= 32 × DST_Width) { PreHorRatio_xx = 32; H_Shift = 5; } else if (SRC_Width >= 16 × DST_Width) { PreHorRatio_xx = 16; H_Shift = 4; } else if (SRC_Width >= 8 ×...
Page 594 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Reserved [27:23] PreHorRatio_Co [22:16] Horizontal ratio of codec pre-scaler Reserved [15:7] PreVerRatio_Co [6:0] Vertical ratio of codec pre-scaler CODEC PRE-SCALER CONTROL REGISTER 2 Register Address Description Reset Value CICOSCPREDST 0x78000054 Codec pre-scaler destination format Initial...
Page 595 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR Vertical scale up/down flag for codec scaler (In 1:1 scale ratio, ScaleUp_V_Co [29] this bit must be “1”) 1: up, 0:down YCbCr Data Dynamic Range Selection for the Color Space Conversion RGB to YCbCr (Codec path) 1 : Wide =>...
Page 596 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE one of YCbCr420, YCbCr422, and RGB 16/18/24 bit format. All source and destination image data must be stored in memory system aligned with word boundary. It means that neither byte nor half-word size DMA operations are supported. Therefore, the width of source and destination image must be selected to satisfy the word boundary condition.
Page 597 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR Figure 20-20 . I/O Timing Diagram for LCD Path Preliminary product information describe products that are in development, 20-32 for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 598: Fifo Mode
S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Memory Memory Video/ Video / 1 Frame Graphic 1 Frame AHB Bus Graphic DMA Mode FIMC Progressive Progressive (CAMIF) Display Controller FIFO Mode FIFO FIFO Full Camera Data Valid Video / Graphic Figure 20-21 . Two input & Two output modes in FIMC...
Page 599 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR Initial CICOSTATUS Description State OvFiY_Co [31] Overflow state of codec FIFO Y OvFiCb_Co [30] Overflow state of codec FIFO Cb OvFiCr_Co [29] Overflow state of codec FIFO Cr Camera VSYNC (This bit can be referred by CPU for first SFR...
Page 600 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW OUTPUT Y3 START ADDRESS REGISTER Register Address Description Reset Value CIPRYSA3 0x78000074 frame start address for preview DMA Initial CIPRYSA3 Description State CIPRYSA3 [31:0] Non-Interleave Y, Interleave YCbCr, RGB : 3 frame start address...
Page 601 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR PREVIEW OUTPUT CB3 START ADDRESS REGISTER Register Address Description Reset Value CIPRCBSA3 0x78000084 frame start address for preview DMA Initial CIPRCBSA3 Description State CIPRCBSA3 [31:0] Cb 3 frame start address for preview DMA PREVIEW OUTPUT CB4 START ADDRESS REGISTER...
Page 602 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW OUTPUT CR3 START ADDRESS REGISTER Register Address Description Reset Value CIPRCRSA3 0x78000094 frame start address for preview DMA Initial CIPRCRSA3 Description State CIPRCRSA3 [31:0] Cr 3 frame start address for preview DMA PREVIEW OUTPUT CR4 START ADDRESS REGISTER...
Page 603 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR 1 : Rotate clockwise 90° Rot90_Pr [13] 0 : Rotator bypass Vertical pixel number of target image for preview DMA. Minimum TargetVsize_Pr [12:0] number is 4. (When Rot90_Pr is set, 8’s multiple but, 4’s multiple if RGB888/666 mode &...
Page 604 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE 1 : enable last IRQ at the end of frame capture (One pulse) LastIRQEn_Pr 0 : normal Interleaved YCbCr 4:2:2 output order memory storing style Order422_Pr [1:0] ※ Interleaved burst length (Interleave YCbCr 4:2:2) Rot90_Pr = 0...
Page 605 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR Y : wanted Main burst length = 2 * Yburst1_Pr, and wanted Remained burst length = 2 * Yburst2_Pr. Cb/Cr : wanted Main burst length = Yburst1_Pr / 2 = Cburst1_Pr, and wanted Remained burst length = Yburst2_Pr / 2 = Cburst2_Pr If Rot90_Pr = 0, no rotation, the wanted burst length is calculated from targetHsize.
Page 606 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW PRE-SCALER CONTROL REGISTER 1 Register Address Description Reset Value CIPRSCPRERATIO 0x780000A4 Preview pre-scaler ratio control Initial CIPRSCPRERATIO Description State SHfactor_Pr [31:28] Shift factor for preview pre-scaler Reserved [27:23] PreHorRatio_Pr [22:16] Horizontal ratio of preview pre-scaler...
Page 607 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR Horizontal scale up/down flag for preview scaler (In 1:1 scale ScaleUp_H_Pr [30] ratio, this bit must be “1”) 1: up, 0:down Vertical scale up/down flag for preview scaler (In 1:1 scale ratio, ScaleUp_V_Pr [29] this bit must be “1”) 1: up, 0:down...
Page 608 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Reserved MainVerRatio_Pr [8:0] Vertical scale ratio for preview main-scaler PREVIEW DMA TARGET AREA REGISTER Register Address Description Reset Value CIPRTAREA 0x780000B0 Preview dma target area Initial CIPRTAREA Description State Reserved [31:26] Target area for preview DMA...
Page 609 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR IMAGE CAPTURE ENABLE REGISTER Register Address Description Reset Value CIIMGCPT 0x780000C0 Image capture enable command Initial CIIMGCPT Description State ImgCptEn [31] camera interface global capture enable capture enable for codec scaler. This bit must be zero in codec...
Page 610 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE CAPTURE CONTROL SEQUENCE REGISTER Register Address Description Reset Value CICPTSEQ 0x780000C4 Camera image capture sequence related FFFF_FFFF CICPTSEQ Description Initial State Cpt_FrSeq [31:0] Capture sequence pattern FFFF_FFFF Cpt_ Fr Ptr Cpt _ Fr Seq [ 31 :0 ] .
Page 611 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR Reserved [25:21] It is used only for FIN is Arbitrary Cb/Cr (Common preview & codec path) ( PAT_Cb/Cr == 8’d128 for GRAYSCALE) PAT_Cb [20:13] 8’d128 Wide CSC Range : 0 ≤ PAT_Cb ≤ 255 Narrow CSC Range : 16 ≤ PAT_Cb ≤ 240...
Page 612 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE DMA start address for Y component (non-interleave YCbCr 4:2:0, 4:2:2) MSCOY0SA [30:0] DMA start address for Interleave YCbCr 4:2:2 / RGB component MSDMA FOR CODEC CB START ADDRESS REGISTER Register Address Description Reset Value MSCOCB0SA...
Page 613 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR MSDMA FOR CODEC CB END ADDRESS REGISTER Register Address Description Reset Value MSCOCB0EN 0x780000E4 MSDMA Cb0 end address related 0000_0000 Initial MSCOCBEND Description State Reserved [31] DMA End address for Cb component (non-interleave YCbCr MSCOCB0END...
Page 614 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Initial MSCOCBOFF Description State Reserved [31:24] Offset of Cb component for fetching source image(non-interleave MSCOCBOFF [23:0] YCbCr 4:2:0, 4:2:2) MSDMA FOR CODEC CR OFFSET REGISTER Register Address Description Reset Value MSCOCROFF 0x780000F4 MSDMA Cr offset related...
Page 615 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR - MSDMA Start address Start address of ADDRStart_Y/Cb/Cr/RGB points the first word address where the corresponding component of Y/Cb/Cr/RGB is read or written. Each one must be aligned with word boundary (i.e. ADDRStart_X[1:0] = 00).
Page 616 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE - MSDMA OFFSET Offset_Y/Cb/Cr/RGB = Memory size for offset per a horizontal line = Number of pixel (or sample) in horizontal offset × ByteSize_Per_Pixel (or Sample) Cf.) ByteSize_Per_Pixel = 1 for YCbCr420 / YCbCr422 (non-interleave)
Page 617 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR Source image format for MSDMA 00 : YCbCr 4:2:0 01 : YCbCr 4:2:2 (non-interleave) InFormat_M_C [2:1] 10 : YCbCr 4:2:2 (interleave) 11 : RGB (cf. RGB format register → InRGB_FMT_Co) MSDMA operation start. (When triggered Low to High by software setting) Hardware doesn’t clear automatically...
Page 618 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE RGB start address, MSDMA Start,End,OFFSET, Preview Target format, MSDMA Source image width, Preview DMA Control MSDMA control etc.. Preview Memory MSDMA Scaler Operation Done Operation Done = EOF signal generation = IRQ signal generation Figure 20-25. SFR & Operation (related each DMA when selected MSDMA input path) Frame start &...
Page 619 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR MSDMA FOR PREVIEW Y0 START ADDRESS REGISTER Register Address Description Reset Value MSPRY0SA 0x78000100 MSDMA Y0 start address related 0000_0000 Initial MSYSA Description State Reserved [31] DMA start address for Y component (non-interleave YCbCr 4:2:0, 4:2:2)
Page 620 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Initial MSPRYEND Description State Reserved [31] DMA End address for Y component (non-interleave YCbCr 4:2:0, 4:2:2) MSPRY0END [30:0] DMA End address for Interleave YCbCr 4:2:2 / RGB component MSDMA FOR PREVIEW CB0 END ADDRESS REGISTER...
Page 621 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR Offset of Y component for fetching source image (non-interleave YCbCr 4:2:0, 4:2:2) MSPRYOFF [23:0] Offset of Interleave YCbCr 4:2:2 / RGB component for fetching source image MSDMA FOR PREVIEW CB OFFSET REGISTER Register Address Description...
Page 622 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE MSDMA Address Change Disable (Only Software trigger mode) ADDR_CH_DIS [30] At the first frame start needs ADDR_CH_DIS = ‘0’ 0 : Address change enable , 1 : Address change disable Reserved [29:28] MSDMA source image vertical pixel size. minimum 8. Also, must...
Page 623 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR MSDMA operation start. (When triggered Low to High by software setting) Hardware clear automatically. This bit is allowed set only Software Trigger mode. If Hardware trigger mode, this bit is read only. ENVID_M_P 1) SEL_DMA_CAM = ‘0’ , ENVID don’t care (using external camera signal for preview path) 2) SEL_DMA_CAM = ‘1’, ENVID is set (0→1) then MSDMA...
Page 624 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Non-interleave Y : 4’s multiple pixel (minimum 4) Interleaved YCbCr 422 / RGB565 : 2’s multiple (minimum 2) RGB666/888 : 1’s multiple (minimum 1) - Initial / Line Cb,Cr (YCbCr 4:2:2 , 4:2:0) Non-interleave Cb / Cr : 8’s multiple pixel (minimum 8)
Page 625 CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR PREVIEW SCAN LINE Y OFFSET REGISTER Register Address Description Reset Value CIPRSCOSY 0x78000138 Preview scan line Y offset related Initial CIPRSCOS Description State Reserved [31:29] The number of the skipped pixels for initial Y offset. scanline Y...
Page 626 S3C6400X RISC MICROPROCESSOR CAMERA INTERFACE Reserved [15:13] The number of the skipped pixels in the screen of the target Line_Croffset_Pr [12:0] image when scan line is changed. Scanline Cr offset can be used when Non-interleaved YCbCr4:2:0 / 4:2:2 Preliminary product information describe products that are in development, 20-61 for which full characterization data and associated errata are not yet available.
Page 627 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR MULTI-FORMAT VIDEO CODEC This chapter describes the function and usages of Multi-Format Video codec in S3C6400X RISC microprocessor. Overview FIMV-MFC V1.0 is a high-performance video codec IP that supports H.263P3, MPEG-4 SP, H.264 and VC-1.
Page 628 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR FIMV-MFC V1.0 video codec is optimized to reduce the logic gate count with sharing large parts of sub- modules for multi-standard. Motion estimation module uses a search RAM to reduce the bandwidth on the external SDRAM.
Page 629 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Features FIMV-MFC V1.0 is a multi-standard video codec IP that can handle the H.263P3, MPEG-4 SP, H.264 BP and VC-1 MP in single codec hardware. The FIMV-MFC V1.0 includes the following features. Multi-standard video codec MPEG-4 part-II simple profile encoding/decoding H.264/AVC baseline profile encoding/decoding H.263 P3 encoding/decoding...
Page 630 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR FIMV-MFC V1.0 embeds 16-bit DSP processor that is dedicated to processing bitstream and controlling the codec hardware. General purpose registers and interrupt for communication between a host processor and the video IP Performance Up to full-duplex VGA 30fps encoding/decoding...
Page 631 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO The Bit Processor This section describes the BIT processor that is optimized to process bitstream in various formats such as MPEG-4, H.263, H.264 and VC-1. The BIT processor is an embedded programmable 16-bit DSP that is highly optimized to handle bitstream data. In addition to processing bitstream, the BIT processor controls the video codec and communicates with a host processor through the host interface.
Page 632: Hardware Acceleration
MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Hardware Acceleration The BIT processor core embeds hardware acceleration sub-modules as followings. Accelerator to support bitstream packing instruction such as put_bits Accelerator to support bitstream unpacking instructions such as get_bits and show_bits Look-up table and searching module for VLC and VLD operation...
Page 633 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Codec firmware In addition to the boot code, a package of the firmware for driving the IP is required. Basically, the package for MPEG-4, H.263P3, H.264 and VC-1 codec is provided. You must write the firmware to a region of external memory and send information about the base address of the region by writing it to the register.
Page 634 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Step 6. if (addr < (80*1024)) go to step 1 else finish downloading Running the codec This section describes how the BIT processor controls the video codec and communicates with a host processor. The provided firmware can handle 8 processes simultaneously. Each process can have difference format –...
Page 635 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Figure 21.5 Codec firmware state diagram Process ID - RunIndex Each process is created with specific ID-named as - range from 0 to 7. Basically, the ID is assigned RunIndex based on the order of creation. After creating processes at initialization step, a host processor commands the BIT processor to execute process specified with the RunIndex.
Page 636 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR (d) VC-1 decoding for bitstream B : RunIndex = 3 Assigning coding format - RunCodStd In addition to the process ID, the is used to define which coding standard is used in created process RunCodStd and whether the created process encodes image or decodes bitstream.
Page 637 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Video codec hardware This section describes the video codec hardware of FIMV-MFC V1.0. All video codec processing except handling coefficients for VLC and VLD are implemented with hardware. Overview H.264 encoder data flow Figure 21.6 highlights the data flow of FIMV-MFC V1.0 H.264 encoding process. The inter-prediction module loads only chrominance data of the reference frame in encoding.
Page 638 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR MPEG-4 encoder data flow Figure 21.7 highlights the data flow of FIMV-MFC V1.0 MPEG-4 encoding process. The data-flow is very similar to the H.264 encoding. The differences are listed below. ― The MPEG-4 encoding process includes the AC/DC prediction instead of the intra-prediction.
Page 639 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Encoder bus loading Table 21.1 Encoder bus loading Item unit No. bytes/pixel row Byte/pixel row No. pixel row/frame Pixel row/picture No bytes/luminance Byte/luminance 101376 307200 345600 Byte/chrominanc No byte/chrominance 50688 153600 172800 No byte/frame Byte/frame 152064 460800 518400...
Page 640 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Bitstream Packing MB/sec 0.375 1.500 1.500 Reconstructed pixel read/write for intra- MB/sec prediction (H.264 case) MPEG-4 Encode MB/sec 21.663 66.012 74.976 * when deblocking filter is enabled H.264 Encode MB/sec 19.022 58.096 65.208 In case of encoding, bus-loading for the H.264 is similar to the MPEG-4’s requirement. It is because FIMV-MFC V1.0 uses only one reference frame in the H.264 encoding and the codec modules reuses reference data in the...
Page 641 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Decoder bus loading Table 21.2 Decoder bus loading Item unit No. bytes/pixel row Byte/pixel row No. pixel row/frame Pixel row/picture No bytes/luminance Byte/luminance 101376 307200 345600 Byte/chrominanc No byte/chrominance 50688 153600 172800 No byte/frame Byte/frame 152064 460800 518400...
Page 642 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Reading reference data for 4x4 block size (H.264 case) MB/se 30.793 93.312 104.976 * It assumes all macroblocks have 4x4 block size. MB/se Writing reconstructed frame 4.562 13.824 15.552 Pixel row read/write for MB/se 3.041...
Page 643 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Ref Read 16x16 (VC-1) MB/sec 7.342 22.248 25.029 Deblocking filter MB/sec 3.041 9.216 10.368 Overlap filter MB/sec 3.041 9.216 10.368 ACDC predictor MB/sec 3.041 9.216 10.368 Write-back for display MB/sec 4.562 13.824 15.552 Write-back for reference MB/sec 4.562 13.824...
Page 644: Frame Buffer
MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Frame buffer This section describes the memory map of the frame buffer used in FIMV-MFC V1.0 video codec module. Base Address for Y frame Frame width in pixel unit Stride line in pixel unit...
Page 645 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Figure 21.10. Frame buffer address map in little endian Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 21-19 Specifications and information herein are subject to change without notice.
Page 646 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR For encoding case, typically, 4 frame buffers are required. These buffers are used for storing incoming image from camera or pre-processor, encoding, storing the currently reconstructed image, and previously reconstructed frame. Rotation/Mirroring FIMV-MFC V1.0 supports rotation together with mirroring function for both incoming image for encoding and output image of the decoder for display.
Page 647 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Figure 21.12. PP rotator data flow Rotation/mirroring modes The Rotator modules support 8-types mode of 90 x n degree(n=0, 1, 2, 3) rotating and mirroring simultaneously. The following table are the supporting rotating /mirroring lists and these represents all possible combinations of rotating and mirroring.
Page 648 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR ROT_LEF_180 Rotate Left 180 (Rotate Right180) Example Image Size : 720x480 ROT_LEFT_270 Rotate Left 270 (Rotate Right 90) Example Image Size : 480x720 MIR_HORIZ Horizontal mirroring Example Image Size : 720x480 MIR_VERT Vertical mirroring...
Page 649 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Motion Estimation The Motion Estimation Block uses full-search algorithm, and the search range is +- 16 pixel or +- 8 pixel. The following features are supported: ― UMV (Unrestricted Motion Vector) mode ― Up to quarter-pel search for H.264-BP ―...
Page 650 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR ME_TOP ME_CORE current picture reference picture for q-pel search ME_DMA reference picture for integer-pel search SDRAM Figure 21.13. Motion Estimation Block Diagram The ME block can impose high-priority on zero motion vector by subtracting calculated SAD by user-defined register value.
Page 651 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Figure 21.14. Motion Estimation Core Block Diagram ME_CORE consist of command interface (ME_CMD_IF), integer-pel search block (FPS), quarter/half-pel search block (QPS) and internal buffers(SW_BUF, RB_BUF, SWH_BUF). ME_CMD_IF block interfaces with BIT processor or CPU. Current frame image is stored in RB_BUF, and reference frame image is stored in SW_BUF and SWH_BUF.
Page 652 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR ME DMA block Figure 21.15. Motion Estimation DMA Block Diagram ME_DMA services current and reference frame images to ME_CORE. SW_DMA and SWH_DMA are reference search window data request channel. SW_DMA and SWH_DMA read data from SDRAM. RB_DMA reads current frame data through Pre-rotator block.
Page 653 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Inter-Prediction The Inter-Predictor uses reconstructed motion vector that represents the displacement between the block currently being decoded and the corresponding location in the reference frame, to calculate interpolated pixel data for motion compensation. The Inter-Predictor consists of main controller, interpolator, DMA and local memory. The role of each sub-block is listed below: It is controlled by the BIT processor that writes control information (motion vector, block mode, reference picture index, picture size and run command etc.) into the...
Page 654 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Control from BIT processor Main Controller spreg64x32 From SDRAM Interpolator (Decoding) dpreg60x96e8 Interpolated data dpreg36x96e8 dpreg36x96e8 spreg64x32e16 From ME spreg64x32e16 local memory Local Buffer Memory (Encoding) Temporal memory Figure 21.16. The Block Diagram of Inter-prediction Figure 21.17 displays the local buffer memory configurations.
Page 655 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO dpreg36x96e8. The local buffer memory contains 1 macroblock pixel data in all block modes. When the macroblock mode is 4x4 block mode, the DMA of inter-predictor read 16 sub-block data from SDRAM(in decoding) and each sub-block is 9x9 because of 6-tap quarter pixel. Because of above mentioned reason, the local buffer memory configuration is 36 pixels(9pixel x 4 sub-block) in horizontal and vertical.
Page 656 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR ME(N) ME(N+1) ME(N+2) Inter-prediction(N) Inter-prediction(N+1) Inter-prediction(N+2) Encoding(N) Encoding(N+1) Encoding(N+2) Copy reference N-th MB,Y Inter-prediction of N-th MB component, from memory of ME Inter-prediction of N-th MB (Y component only) (U&V components) to memory of intra-predictor Load reference N-th MB,U&V components,...
Page 657 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Intra-Prediction FIMV-MFC V1.0 includes two intra-prediction modules. One is for the MPEG-4/H.263P3 AC/DC prediction and the other for the H.264 intra-prediction. Figure 6.x highlights the data flow of intra-prediction in the MPEG-4 and the H.264. In case of H.263P3 AIC (Advanced Intra Coding) mode, the AC/DC prediction is performed for the transformed coefficient, not for quantized coefficient.
Page 658 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Figure 21.22. Intra-prediction block diagram In case of MPEG-4 encoding, the hardwired prediction mode decision is used. It brings high performance and low power consumption. The coefficient data of both encoding and decoding is re-ordered automatically based on the detected prediction mode.
Page 659 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Figure 21.23. Portion of the pixels which are stored in the neighboring pixel buffer The DMA controller stores or loads 32 coefficients per macroblock when the MPEG-4/H.263P3 is enabled. The required memory space is (number_of_macroblock_in_width_of_picture * 32) words. The memory space for those coefficients is assigned by the BIT processor within the working buffer defined in the 3.2.
Page 660 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Transform/Quantization FIMV-MFC V1.0 has two transform/quantization modules. One is for the MPEG-4/H.263P3, the other for the H.264. FIMV-MFC V1.0 H.264 T/Q block processes transform and quantization (or inverse transform and inverse quantization) of residual data. T/Q block compresses the residual data and send to other blocks (Coefficient buffer, Motion compensation block).
Page 661 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO TQ_CTRL controls encode and decode processing of the H.264 T/Q block. Figure 21.25. H.264 tranform/quantization block diagram MPEG-4/H.263 The MPEG-4/H.263P3 transform/quantization module supports only the method1 quantization mode for MPEG-4 bitstream. It can process the AIC (Advanced Intra Coding) and the modified quantization mode for H.263P3 bitstream.
Page 662 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Figure 21.26 highlights the MPEG-4/H.263 transform/quantization process in a macroblock pipeline. In the encoding process, the quantized coefficients are sent to the inverse quantization module and the coefficient buffer interface at the same time. The coefficients in the coefficient buffer are processed again in the AC/DC prediction module.
Page 663 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Overlap-smoothing/Deblocking Filter Overview Deblocking filter removes blocking artifacts resulted from quantization, different motion vectors. The filter processing is applied in both decoder and encoder. FIMV-MFC V1.0 deblocking filter supports H.264/H.263/MPEG4. For H.264 and H263, the deblocking filter operates within coding loop. Filtered frames are used as reference frames for motion compensation of subsequent coded frames.
Page 664 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR mode improves the bandwidth efficiency. Figure 21.29 Figure 21.29 illustrates the pipeline structure of the decoding case that is applied to both the H.263 and the H.264. The number between brackets means the macroblock address is being processed.
Page 665 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Block diagram The figure 21.30 highlights the overlap/deblocking filter architecture. The filtered pixel data are stored in working buffer. The output data is store to output buffer. The rotator/mirror block will read this output buffer. The input buffer and DMA buffer is used to store/load the intermediate data for processing deblock/overlap filter.
Page 666 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR H.264 Deblocking filter A filtering shall be applied to all 4x4 block edges of a picture, except edges at the boundary of the picture. The filtering is performed on a macroblock basis and processed in order of increasing macroblock addresses. For each macroblock, vertical edges are filtered first, from left to right, and then horizontal edges are filtered from top to bottom.
Page 667 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO H.263 Annex J Deblocking filter The filtering is performed on 8x8 block edges, except across picture edge. The horizontal edges are filtered first from top to bottom, and then vertical edges are filtered from left to right. The pixels that are used in filtering across a horizontal edge need not be influenced by previous filtering across a vertical edge.
Page 668 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR VC-1 Overlap-smoothing filter VC-1 overlap-smoothing filtering shall be performed subsequent to decode the frame, and prior to deblocking filter. The edges of an 8x8 block that separate two intra blocks are filtered. Vertical edges will be filtered first, followed by the horizontal edges. Subsequent to filtering, the constant value of 128 will be added to each pixel of the block, which will be clamped to the range [0 255] to produce the reconstructed output.
Page 669 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO VC-1 Deblocking filter VC-1 deblocking filtering process operates on the pixels that border neighboring blocks. The block boundaries may occur at every 4 , 12 , etc pixel row or column in P pictures. Filtering the I pictures occurs at every 8 , 24 , etc pixel row and column.
Page 670 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR MPEG-4 Deblocking filter for post-processing FIMV-MFC V1.0 can apply deblocking filtering for the MPEG-4 decoded image using either H.264-like filtering or H.263-like filtering operation. The BIT processor generates parameters suitable for selected mode based on the result from the MPEG-4 decoding process.
Page 671 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Coefficient Buffer Interface The coefficient buffer interface provides a channel for the BIT processor to read quantized coefficients resulted from encoding process or to send variable-length-decoded coefficients to the video codec module for decoding process. The coefficient buffer interface also performs reordering of coefficients based on the scan type. Block diagram Figure 21.35 illustrates the block diagram of the coefficient buffer interface.
Page 672 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Reordering coefficients Reordering is performed based on scan types set by the BIT processor. The scan types are listed below. H.264 The H.264 baseline profile uses only the zig-zag scan type. MPEG-4/H.263P3 The MPEG-4/H.263P3 uses 3 scan types zig-zag, alternative horizontal, and alternative vertical scan type.
Page 673 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Encoder operation In case of encoding, quantized coefficients are written to the internal memory of the coefficient buffer interface without any reordering. When the BIT processor reads the coefficients, they are reordered and the flags that indicate corresponding coefficient has a non-zero value are sent to the BIT processor to check if there is coefficient to be encoded.
Page 674 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Decoder operation The BIT processor writes decoded coefficient without reordering-inverse zig-zag scanning. The reordering process is performed when the inverse quantization module reads coefficients from the coefficient buffer interface. The sub-modules such as the quantizer and AC/DC predictor handles zero if corresponding flag of coefficient is zero.
Page 675 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Macroblock Controller FIMV-MFC V1.0 has a complex and large number of pipeline for high-performance. To manage it wholly by the BIT processor is not suitable. Therefore, FIMV-MFC V1.0 embeds the macroblock controller to control all sub module of the video codec based on the configuration of pipelining by the BIT processor.
Page 676 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR FIMV-MFC V1.0 Programming Model ( Special Function Register ) The FIMV-MFC V1.0 is communicated with a host processor through the APB bus interface. Table 21.4 illustrates the address map of the region that could be accessed via the APB.
Page 677 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO The host interface registers BIT Processor’s registers are divided into 2 categories. Address 0x000 ~ 0x0FC (64 registers address space) are H/W registers. These registers have reset values and the functions are fixed (not configurable). Address 0x100 ~ 0x1FC (64 registers) are general purpose S/W registers.
Page 678 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Summary of host interface registers Table 21.5. BIT Processor Common Register Summary (BASE = 0x7E002000) Reset Address Type Width Name Description value BASE+0x000 CodeRun BIT run start BASE+0x004 CodeDownLoad Code Download Data register BASE+0x008...
Page 679 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO BASE+0x12C BitStreamWrPtr1 Bit Stream Buffer Write Address of Run Index 1 BASE+0x130 BitStreamRdPtr2 Bit Stream Buffer Read Address of Run Index 2 BASE+0x134 BitStreamWrPtr2 Bit Stream Buffer Write Address of Run Index 2 BASE+0x138 BitStreamRdPtr3 Bit Stream Buffer Read Address of Run Index 3 BASE+0x13C BitStreamWrPtr3...
Page 680 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Table 21.6. DEC_SEQ_INIT Parameter Register Summary DEC_SEQ_INIT Address Type Name Description INPUT BASE+0x180 CMD_DEC_SEQ_BIT_BUF_START Bitstream Buffer Address ARGUMENT BASE+0x184 CMD_DEC_SEQ_BIT_BUF_SIZE Bitstream Buffer Size BASE+0x188 CMD_DEC_SEQ_OPTION5 Decoding sequence option BASE+0x18C CMD_DEC_SEQ_PRO_BUF Process Buffer Address BASE+0x190...
Page 681 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Table 21.7. ENC_SEQ_INIT Parameter Register Summary ENC_SEQ_INIT Address Type Name Description INPUT BASE+0x180 CMD_ENC_SEQ_BIT_BUF_START Bitstream Buffer Address ARGUMENT BASE+0x184 CMD_ENC_SEQ_BIT_BUF_SIZE Bitstream Buffer Size BASE+0x188 CMD_ENC_SEQ_OPTION Encoding sequence option BASE+0x18C CMD_ENC_SEQ_COD_STD Encode Coding Standard BASE+0x190 CMD_ENC_SEQ_SRC_SIZE Encode Source Frame Size BASE+0x194 CMD_ENC_SEQ_SRC_F_RATE...
Page 682 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR BASE+0x1DC CMD_ENC_SEQ_TMP_BUF_4 Temporary Buffer4 Address OUTPUT BASE+0x1C0 RET_ENC_SEQ_SUCCESS Command executing result status RETURN Table 21.8. DEC_PIC_RUN Parameter Register Summary DEC_PIC_RUN Address Type Name Description INPUT BASE+0x180 CMD_DEC_PIC_ROT_MODE Display frame post-rotator mode ARGUMENT BASE+0x184 CMD_DEC_PIC_ROT_ADDR_Y...
Page 683 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO BASE+0x1C8 RET_DEC_PIC_ERR_MB_NUM Error MB number in decoded picture BASE+0x1CC RET_DEC_PIC_TYPE Decoded picture type BASE+0x1D8 RET_DEC_PIC_SUCCESS Command executing result status Table 21.9. ENC_PIC_RUN Parameter Register Summary ENC_PIC_RUN Address Type Name Description INPUT BASE+0x180 CMD_ENC_PIC_SRC_ADDR_Y Input source frame buffer Y SDRAM address ARGUMENT BASE+0x184...
Page 684 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR ARGUMENT BASE+0x184 CMD_SET_FRAME_BUF_STRIDE Frame Buffer Line Stride OUTPUT RETURN Table 21.11. ENC HEADER Parameter Register Summary ENC_HEADER Address Type Name Description INPUT BASE+0x180 CMD_ENC_HEADER_CODE Header code to be encoded ARGUMENT OUTPUT RETURN Table 21.12. DEC PARA SET Parameter Register Summary...
Page 685 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Table 21.14. GET F/W VER Parameter Register Summary GET_F/W_VER Address Type Name Description INPUT ARGUMENT OUTPUT BASE+0x1C0 RET_GET_FW_VER Returned Version Code with following format: RETURN [31:16]: Product No (0xF202) [15:0]: Ver. No. (0xMmrr) for M.m.rr Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 686 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Detailed Description of BIT Processor Registers CodeRun (0x000) Name Type Function Reset Value CodeRun 0 – BIT Processor stop execution 1 – BIT Processor start execution CodeDownLoad (0x004) Name Type Function Reset Value 15:0...
Page 687 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO BitCodeReset (0x014) Name Type Function Reset Value CodeReset If host write ‘1’ to this register, program counter of BIT is set to “0” Therefore restart at initial routine BitCurPc (0x018) Name Type Function Reset Value 13:0 CurPc Current program counter of BIT processor.
Page 688 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR BitStreamCtrl (0x10C) Name Type Function Reset Value SelBigEndian 0 – bit stream buffer is 4 byte little endian format 1 – bit stream buffer is big endian BufStsCheckDis 0 – bit stream buffer overflow/underflow check enable 1 –...
Page 689 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO If this flag is “1”, [BufPicFlush] bit is ignored. In decoding case, this flag is ignored. FrameMemCtrl (0x110) Name Type Function Reset Value SelBigEndian 0 – frame memory is 4 byte little endian format 1 – frame memory is big endian DecFuncCtrl (0x114) Name Type...
Page 690 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR BitWorkBufCtrl (0x11C) Name Type Function Reset Value WorkBufConfig 0 – Work Buffer configurable setting disable 1 – Work Buffer configurable setting enable BitStreamRdPtr0 (0x120) Name Type Function Reset Value 31:0 StreamRdPtr0 In decode case, current external SDRAM Bit Stream Buffer read address of process index 0 is set to this register by BIT processor.
Page 691 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO BitStreamRdPtr1 (0x128) Name Type Function Reset Value 31:0 StreamRdPtr1 External SDRAM Bit Stream Buffer read address of process index 1. BitStreamWrPtr1 (0x12C) Name Type Function Reset Value 31:0 StreamWrPtr1 External SDRAM Bit Stream Buffer write address of process index 1.
Page 692 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR BitStreamRdPtr4 (0x140) Name Type Function Reset Value 31:0 StreamRdPtr4 External SDRAM Bit Stream Buffer read address of process index 4. BitStreamWrPtr4 (0x144) Name Type Function Reset Value 31:0 StreamWrPtr4 External SDRAM Bit Stream Buffer write address of process index 4.
Page 693 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO BitStreamRdPtr7 (0x158) Name Type Function Reset Value 31:0 StreamRdPtr7 External SDRAM Bit Stream Buffer read address of process index 7. BitStreamWrPtr7 (0x15C) Name Type Function Reset Value 31:0 StreamWrPtr7 External SDRAM Bit Stream Buffer writes address of process index 7.
Page 694 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR 3’b100 (SET_FRAME_BUF): Set decoded/ reconstructed frame buffer SDRAM address and maximum frame buffer number. Before encode/decode picture run command, host must inform frame buffer SDRAM address to BIT processor then BIT processor arrange frame buffer...
Page 695 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO RunCodStd (0x16C) Reset Name Type Function Value CodStd Host writes the codec standard index code to this register before every writing run command 3’b000 : MPEG4/H.263 DECODER 3’b001 : MPEG4/H.263 ENCODER 3’b010 : H.264 DECODER 3’b011 : H.264 ENCODER 3’b100 : VC-1 DECODER IntEnable (0x170)
Page 696 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR IntReason (0x174) Reset Name Type Function Value 15:0 IntReason Interrupt Reason Flag register. Each bit of this register is interrupt report flag of each interrupt. “1” means interrupt is generated and “0” means not generated. BIT writes “1” to the bit of each...
Page 697 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO The decoded image (prior to de-blocking filter) is also stored for future motion compensation reference. This flag is valid only for MPEG4 / H.263 case. When H.263 case, if Annex J is turned on, this flag is ignored and H.263+ Annex J de-blocking filter is performed.
Page 698 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR CMD_DEC_SEQ_PRO_BUF (0x18C) Name Type Function Command 31:0 ProcessBufAddr Process buffer SDRAM byte address DEC_SEQ_I Process buffer must be 256 byte-aligned. Host must write this register before executing DEC_SEQ_INIT command Process buffer is used as PS data save buffer for AVC and MV direct prediction buffer for VC1 and not used for mpeg4.
Page 699 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO CMD_DEC_SEQ_TMP_BUF_2 (0x194) Name Type Function Command 31:0 TempBufAddr Temporary buffer SDRAM byte address DEC_SEQ_I Temporary buffer must be 256 byte-aligned. Host must writes this register before executing DEC_SEQ_INIT command Temporary buffer 2 is used as data partition part 1 save buffer for mpeg4 and Intra prediction Cb buffer for AVC and deblocking buffer for VC1.
Page 700 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR buffer for AVC and not used for VC1 and mpeg4. Max size of temporary buffer 4 is MB number * 8 for AVC. CMD_DEC_SEQ_TMP_BUF_5 (0x1A0) Name Type Function Command 31:0 TempBufAddr Temporary buffer SDRAM byte address DEC_SEQ_I Temporary buffer must be 256 byte-aligned.
Page 701 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO RET_DEC_SEQ_SRC_F_RATE (0x1C8) Name Type Function Command 15:0 FrameRateRes Decoded picture frame rate residual DEC_SEQ_I Number of time units of a clock operating at the frequency [FrameRateDiv] Hz For example, [FrameRateDiv] = 30000 and [FrameRateRes] = 1001 then video frame rate = 30000 / 1001 = 29.97 Hz [FrameRateDiv] = 1 and [FrameRateRes] = 15 then video frame rate = 15 / 1 = 15 Hz...
Page 702 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR RET_DEC_SEQ_FRAME_DELAY (0x1D0) Name Function Command FrameBufDelay Maximum display frame buffer delay for buffering DEC_SEQ_I decoded picture reorder. BIT processor may delay decoded picture display for display reordering when H.264, pic_order_cnt_type “0” or “1” case or VC-1 decode case.
Page 703 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO H.263 Annex J 0 – Annex J off 1 – Annex J On CMD_ENC_SEQ_BIT_BUF_START (0x180) Name Type Function Command 31:0 BitBufAddr Bitstream buffer SDRAM byte address ENC_SEQ_I Bitstream buffer must be 512 byte-aligned. Host must write this register before executing ENC_SEQ_INIT command CMD_ENC_SEQ_ E (0x184) Name...
Page 704 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR AUDEnable Encode H.264 Access Unit Delimiter RBSP enable If this flag is “1”, BIT encodes Access Unit Delimiter RBSP at every start of picture. Access Unit Delimiter RBSP is used to simplify the detection of the picture boundary This flag is ignored at MPEG4/H.263 encode case.
Page 705 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO CMD_ENC_SEQ_COD_STD (0x18C) Name Type Function Command EncCodStd Encode Coding Standard ENC_SEQ_I 0 – MPEG4 Simple Profile 1 – MPEG4 Short Video Header / H.263+ 2 – H.264 Host must writes this register before executing SEQ_INIT command CMD_EMC_SEQ_SRC_SIZE (0x190) Name Type...
Page 706 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR CMD_ENC_SEQ_MP4_PARA (0x198) Name Type Function Command DataPartEn 0 - Data Partition Disable ENC_SEQ_ INIT 1 – Data Partition Enable RevVlcEn 0 – Normal VLC table used 1 – Reversible VLC table used This bit is ignored if DataPartEn bit is ‘0’...
Page 707 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO … 0_1100 : +12 ConstIntraFlag constrained_intra_pred_flag in Picture Parameter 0 – intra prediction use inter MB data 1 – intra prediction does not use inter MB data DisableDeblk disable_deblocking_filter_idc in slice header 0 – enable deblocking filter 1 –...
Page 708 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR This bit is ignored if SliceMode bit is 0 In H.263 Mode with Annex K = 0, this bit is ignored 15:2 SliceSizeNum If SliceSizeMode is 0, macro-block number of one slice must be set to this register...
Page 709 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO 0 : do not check Reference decoder buffer delay constraint SkipDisable Rate control automatic skip disable If this flag is “0”, BIT processor may skip one picture if available bits are insufficient for accommodate the bit budget.
Page 710 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR CMD_ENC_SEQ_FMO (0x1B8) Name Type Function Command FmoEnable 0: FMO disable ENC_SEQ_INIT 1: fmo enable FmoSliceNr Number of Slice Groups (It must be a value between 2 and 8. FmoType13 0: Type0 (interleaved) 1: Type1 (Dispersed)
Page 711 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO AVC. Temporary buffer 2 must be larger than (stride/2)*(picheight/2)/8 for AVC. In case of mpeg4, temporary buffer 2 size is not estimated. CMD_ENC_SEQ_TMP_BUF_3 (0x1D8) Name Type Function Command 31:0 TempBufAddr Temporary buffer SDRAM byte address ENC_SEQ_I Temporary buffer must be 256 byte-aligned.
Page 712 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR CMD_ENC_SEQ_TMP_BUF_4 (0x1DC) Name Type Function Command 31:0 TempBufAddr Temporary buffer SDRAM byte address ENC_SEQ_I Temporary buffer must be 4 byte-aligned. Host must write this register before executing ENC_SEQ_INIT command Temporary buffer 4 is used when FMO option is enabled in H.264 encoder.
Page 713 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO PostRotEn Post rotation enable If this field is “1”, the rotated image is stored to DecPicRotAddrY, DecPicRotAddrCb, DecPicRotAddrCr address addition to decoded image store for future reference. If this field is “0”, the post rotation is disabled and PostRotMode field is ignored.
Page 714 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR CMD_DEC_PIC_ROT_ADDR_CB (0x188) Comman Name Type Function 31:0 DecRotAddrCb Rotated display frame address of Cb DEC_PIC_ In VC-1 mode, this register is not used. The rotated output will be one of the frames which previously allocated by RET_DEC_SEQ_FRAME_NEED(0x1CC).
Page 715 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO CMD_DEC_PIC_ROT_STRIDE (0x19C) Comman Name Type Function 10:0 DecRotStride Rotated display frame Stride DEC_PIC_ CMD_DEC_PIC_CHUNK_SIZE (0x1A8) Comman Name Type Function 31:0 DecPicChunkSize Byte size of picture stream data DEC_PIC_ This value will be only valid in file-play mode, and it will be used as size of stream data when BIT processor update write pointer of picture stream buffer.
Page 716 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR RET_DEC_PIC_FRAME_NUM (0x1C0) Comman Name Type Function 15:0 DecFrameNum Decoded frame number. DEC_PIC_ After BIT decodes one frame, BIT increase frame number and then stores frame number to this register. RET_DEC_PIC_IDX (0x1C4) Comman Name Type...
Page 717 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO RET_DEC_PIC_TYPE (0x1CC) Comman Name Type Function DecPicType The picture type of current decoded picture. DEC_PIC_ 0 – I (Intra) picture 1 – P (Inter) picture. RET_DEC_PIC_SUCCESS (0x1D8) Comman Name Type Function RetStatus 0 – DEC_PIC_RUN command executed with DEC_PIC_ error 1 –...
Page 718 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR CMD_ENC_PIC_SRC_ADDR_CB (0x184) Comman Name Type Function 31:0 SrcAddrCb Encoding source frame address of Cb ENC_PIC_ CMD_ENC_PIC_SRC_ADDR_CR (0x188) Comman Name Type Function 31:0 SrcAddrCr Encoding source frame address of Cr ENC_PIC_ CMD_ENC_PIC_QS (0x18C) Comman Name...
Page 719 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO RotAng[1:0] 0 : 0 degree counterclockwise rotate 1 : 90 degree counterclockwise rotate 2 : 180 degree counterclockwise rotate 3 : 270 degree counterclockwise rotate If this field is 4’b0000, pre-rotation is disabled. PreRotEn Pre-rotation enable If this field is “1”, the source image is rotated prior to encoding, If this field is “0”, the pre-rotation is disabled and...
Page 720 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR picture automatically. After encoding IDR picture, I picture period calculation is reset to initial state. For example, if host set [IdrPic] flag set 18th frame and [EncGopNum] is 15, encoded picture types are 1st frame : I (IDR - automatically)
Page 721 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO RET_ENC_PIC_TYPE (0x1C4) Comman Name Type Function EncPicType The picture type of current encoded picture. ENC_PIC_ 0 – I (Intra) picture 1 – P (Inter) picture. RET_ENC_PIC_IDX (0x1C8) Comman Name Type Function 15:0 RecPicIdx Reconstructed frame index ENC_PIC_ After BIT encodes one frame, BIT return reconstructed frame index to this register...
Page 722 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Host must set the associated frame buffer SDRAM address (Y, Cb, Cr) to SDRAM buffer of address [ParaBufAddr] CMD_SET_FRAME_BUF_STRIDE (0x184) Name Type Function Command 10:0 LineStride Line stride offset of picture frame memory SET_FRAM...
Page 723 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO CMD_ENC_PARA_SET_TYPE (0x180) Name Type Function Command EncParaSetType Parameter set type ENC_PARA _SET 0 – Sequence Parameter Set 1 – Picture Parameter Set RET_ENC_PARA_SET_SIZE (0x1C0) Name Type Function Command EncParaSetSize Encoded Sequence/Picture parameter set RBSP byte ENC_PARA size _SET...
Page 724 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR BIT Processor operations Description of BIT Processor Registers These host interface registers can be partitioned into three categories according to their usage as listed below: BIT Processor Control Registers: Host interface registers in this category will be used to update or show BIT processor status to host processors.
Page 725 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO For example, two processes (MPEG4 Decoder, H.264 Encoder) run simultaneously (full duplex case). If host executes ENC_PIC_RUN command after DEC_PIC_RUN command, BIT processor needs H.264 encoding code image to execute H.264 encoding a picture, therefore it loads automatically H.264 encoding code image from SDRAM (context switching).
Page 726 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR In decoder case, host writes the bit stream to be decoded then BIT processor reads the bit stream. In this case, the bit stream overwriting or underflow may occur and if it occurs, decoding will fail. To prevent overwriting or underflow, current bit stream read/write pointer must be exchanged between host and BIT processor.
Page 727 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Description of Run Commands The command arguments registers must be set by host prior to executing the command. After completion of command, return parameter registers are available to host. Host must set command at BusyFlag register is “0”. After BIT processor acknowledges new command, BusyFlag register is “1”...
Page 728 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR command argument register. SET_FRAME_BUF This command informs frame buffer addresses to be used as a decoding/reconstructing image to BIT processor. Total 63 frame buffers may be used for decoding/reconstructing. The minimal number of frame buffers required for successful decoding is informed by RET_DEC_SEQ_FRAME_NEED register.
Page 729 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO This command encodes the specific header. The sequence headers must be encoded at start of bit stream and BIT processor encodes the sequence header at ENC_SEQ_INIT command. In some application like video telephony the sequence headers must be transferred for error resilience or decoder refreshment. In this case host set ENC_HEADER command between ENC_PIC_RUN commands to insert the specific header in the bit stream.
Page 730 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR This is the output return data for ENC_PIC_RUN command. If [MbBitReport] flag in CMD_ENC_SEQ_OPTION register is “1”, BIT processor stores the start bit position of each macro block from the beginning of picture to the parameter buffer after ENC_PIC_RUN command completion.
Page 731 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Sequence/Picture parameter set RBSP This is the input argument for DEC_PARA_SET command or the output encoded RBSP stream for ENC_PARA_SET. Working Buffer Management This area is used for internal working buffer in SDRAM for encoding/decoding operation. For example, the reconstructed pixel row buffer for MPEG4 AC/DC prediction or H.264 intra prediction, context saving buffer for running multiple processes, bit stream re-ordering buffer for MPEG4 data partition or H.264 FMO/ASO and so on.
Page 732 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Type Name Description Size (KB) STATIC_PRC_DMEM BIT processor data memory of each process for context switching STATIC STATIC_PRC_SEQ Static data storage of each sequence MP4_DEC_ACDC AC/DC prediction buffer of picWidth*8 Y/Cb/Cr TEMP_PIC MP4_DEC_DP1 Bit stream reordering...
Page 733 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO VC1_DEC VC1_DEC_DEBLK Overlap/deblock filter working buffer VC1_DEC_DIRECTMV DirectMV working buffer AVC_ENC_IP Intra prediction buffer of TEMP_PIC Y/Cb/Cr AVC_ENC AVC_ENC_FMO FMO group status buffer The static buffer is used commonly in whole processes/codecs and temporal picture buffer is re-used by each process (codec).
Page 734 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR MP4_DEC_ACDC AC/DC prediction buffer of picWidth*8 Y/Cb/Cr TEMP_PI MP4_DEC_DP1 Bit stream reordering buffer for data partition MP4_DEC MP4_DEC_DP2 Bit stream reordering buffer for data partition MP4_ENC_ACDC AC/DC prediction buffer of picWidth*8 Y/Cb/Cr TEMP_PI MP4_ENC_DP1...
Page 735 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO VC1_DEC VC1_DEC_DEBLK Overlap/deblock filter working buffer According to the requirements of target application, application could reserve Work Buffer space by selecting the sub-set of the buffers presented in this table. Description of Run Process BIT processor can execute maximum 8 processes simultaneously. Each process may have different Codec Standard (MPEG4 DECODE, H.264 ENCODE, etc.).
Page 736 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR In case of the pre-rotator, the mirroring fields are applied prior to rotating then a counterclockwise rotating is applied to horizontal/vertical flipped image. In case of the post-rotator, the rotation field is applied prior to horizontal/vertical mirroring then mirroring is applied to counterclockwise rotated image.
Page 737 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Example of Single MPEG4 Decoder Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 21-111 Specifications and information herein are subject to change without notice.
Page 738 MULTI-FORMAT VIDEO CODEC S3C6400X RISC MICROPROCESSOR Example of Single H.264 Encoder Preliminary product information describe products that are in development, 21-112 for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 739 FIMV-MFC V1.0 MULTI-FORMAT CODEC VIDEO Example of H.264 Full Duplex Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 21-113 Specifications and information herein are subject to change without notice.
Page 740 S3C6400X RISC MICROPROCESSOR JPEG CODEC JPEG CODEC This chapter describes the functions and usage of JPEG CODEC in S3C6400. OVERVIEW The JPEG codec core is composed of control circuit, DCT/quantization, Huffman coder, marker process block, and AHB slave interface control as shown in Figure 22-1. Both input/output image data bus and compressed data bus are 8-bits.
Page 741: Functional Descriptions
JPEG CODEC S3C6400X RISC MICROPROCESSOR BLOCK DIAGRAM Huffman coder & & Quantization marker process Quantization Huffman Table Table Control circuit & internal registers & AHB interface Encoding) JPG file YUV4:2:2 JPEG (YUV4:2:2 RGB565 Codec YUV4:2:0) Decoding) JPG file (YUV4:4:4 JPEG...
Page 742 S3C6400X RISC MICROPROCESSOR JPEG CODEC process is performed over the DCT coefficients by utilizing the quantization tables. During decoding, dequantization will be done and then DCT coefficients will be transformed into the image data. HUFFMAN CODER AND MARKER PROCESS Variable-length encoding and decoding are done based on Huffman table.
Page 743 JPEG CODEC S3C6400X RISC MICROPROCESSOR Figure 22-2. Access Order in Quantizer Table INTERRUPT SIGNAL Interrupt signal will be generated under the following conditions (the register, JPGIRQ, which identifies causes) 1. Compression or decompression process for one frame is completed, 2. JPGIRQ[3] is set high during decompression when the registers storing the image size and sampling factor are ready to be read out after the marker analysis.
Page 744 S3C6400X RISC MICROPROCESSOR JPEG CODEC Table 22-1. Markers at JPEG CODEC Marker Codes(Hex) Description FFD8 Start of image FFC0 Baseline DCT FFDA Start of scan FFDB Define quantization table FFC4 Define Huffman table FFDD Define restart interval RSTm FFD0~FFD7 Restart with module 8 count “m”...
Page 745 JPEG CODEC S3C6400X RISC MICROPROCESSOR JPGDRI Reset interval registers Essential JPGY Vertical size register Essential JPGX Horizontal size register Essential QTBL0 Quantizer table0 entry register. Essential QTBL1 Quantizer table1 entry register Essential QTBL2 Quantizer table2 entry register Essential QTBL3 Quantizer table3 entry register...
Page 746 S3C6400X RISC MICROPROCESSOR JPEG CODEC BASIC JPEG ENCODING SEQUENCE Encoding Start IMG_ADDRx Set JPGMOD HUF_ADDRx Set JPGDRI MISC Set JPGGHNO SW_JSTART JPGY & JPGX MAIN_IRQ is high ? COEFFx Read JPGCNT & JPGSTS QTABLE Encode more frames ? HTABLE Encoding Start Figure 22-4.
Page 747 JPEG CODEC S3C6400X RISC MICROPROCESSOR JPEG DECODING SEQUENCE: SOFTWARE CONTROLLED DECODING Start Decoding proc. Set JPGMOD IMG_ADDRx Read JPGIRQ HUF_ADDRx SW_JRSTART MISC MAIN_IRQ is high ? SW_JSTART Read JPGSTS HD_IRQ is high ? Decoding more frame? Encoding proc. Finished Figure 22-5. Example flow chart of software controlled decoding Take the following steps for software controlled JPEG decoding: 1.
Page 748 S3C6400X RISC MICROPROCESSOR JPEG CODEC 9. You must read JPGIRQ and JPGSTS registers to clear internal pended IRQs. JPEG DECODING SEQUENCE: HARDWARE CONTROLLED DECODING (ONLY 1 FRAME) Start Decoding proc. Set JPGMOD IMG_ADDRx HUF_ADDRx JPGCON MISC SW_JSTART Decoding more frame?
Page 749 JPEG CODEC S3C6400X RISC MICROPROCESSOR JPEC CODEC SPECIAL REGISTERS Table 22-3 Register summary of JPEG Codec Register Address Description Reset Value JPGMOD 0x78800000 Process mode register. 0x00000000 JPGSTS 0x78800004 Operation status registers. 0x00000000 Quantization table number register and JPGQHNO 0x78800008 0x00000000 Huffman table number register.
Page 750 S3C6400X RISC MICROPROCESSOR JPEG CODEC 0x7880083C 0x78800840 Group number of the order for occurrence HDCTBLG0 (12 data with the distance of 4 on address) 0x7880086C 0x78800880 The number of code per code length (16 HACTBL0 data with the distance of 4 on address)
Page 751 JPEG CODEC S3C6400X RISC MICROPROCESSOR SW_JRSTART 0x78801014 Restart JPEG process 0x00000000 S_RESET_CON 0x78801018 SW Reset JPEG 0x00000001 JPG_CON 0x7880101C JPEG control register 0x00000000 Coefficient values for RGB ↔ YCbCr COEF1 0x78801020 0x00000000 converter Coefficient values for RGB ↔ YCbCr COEF2...
Page 752 S3C6400X RISC MICROPROCESSOR JPEG CODEC JPGSTS Register Address Description Reset Value JPGSTS 0x78800004 Operation status registers. 0x00000000 JPGSTS Description Reserved Reserved [31:1] Process mode. Status 1: Normal Operation isn’t done. 0: Normal Operation is done. JPGQHNO Register Address Description Reset Value...
Page 753 JPEG CODEC S3C6400X RISC MICROPROCESSOR JPGDRI Register Address Description Reset Value JPGDRI 0x7880000C MCU, which inserts RST marker. 0x00000000 JPGDRI Description Reserved Reserved [31:16] It is the reset interval that identifies the distance between two Restart_Interval [15:0] adjacent RST markers in terms of MCU Note: It is valid only in compression.
Page 754 S3C6400X RISC MICROPROCESSOR JPEG CODEC JPGCNT Register Address Description Reset Value JPGCNT 0x78800018 The amount of the compressed data in bytes 0x00000000 JPGCNT Description Reserved Reserved [31:24] B_COUNT [23:0] It defines the byte of compressed data count in the width of 24 bits.
Page 755 JPEG CODEC S3C6400X RISC MICROPROCESSOR Reserved Reserved Bitstream error status. Valid during Decompression only. Bitstre_err_status 0: There is no syntax error on the compressed file. 1: There is syntax error on the compressed file. Header status. Valid during Decompression only.
Page 756 S3C6400X RISC MICROPROCESSOR JPEG CODEC QTBL1 Description Reserved Reserved [31:8] It defines the quantizer table 1. The user must write some value in Q_val1 [7:0] this. Note: Address offset is increased as 0x04(word addressing). QTBL2 Register Address Description Reset Value...
Page 757 JPEG CODEC S3C6400X RISC MICROPROCESSOR HDCTBL0 Register Address Description Reset Value 0x78800800 The number of code per code length (16 data with HDCTBL0 the distance of 4 on address) 0x7880083C HDCTBL0 Description Reserved Reserved [31:8] It defines the number of code per code length in DC Huffman table...
Page 758 S3C6400X RISC MICROPROCESSOR JPEG CODEC HACTBL0 Description Reserved Reserved [31:8] It defines the number of code per code length in AC Huffman table H_AC_val0 [7:0] 0. The user must write some value in this. Note: Address offset is increased as 0x04(word addressing).
Page 759 JPEG CODEC S3C6400X RISC MICROPROCESSOR HDCTBLG1 Register Address Description Reset Value 0x78800C40 Group number of the order for occurrence (12 data with the distance of 4 on address) HDCTBLG1 8-bits register 0x78800C6C HDCTBLG1 Description Reserved Reserved [31:8] It defines the group number of the order for occurrence in DC...
Page 760 S3C6400X RISC MICROPROCESSOR JPEG CODEC HDCTBLG1 Description Reserved Reserved [31:8] It defines the group number of the order for occurrence in AC H_AC_G_val1 [7:0] Huffman table 1. The user must write some value in this. Note: Address offset is increased as 0x04(word addressing).
Page 761 JPEG CODEC S3C6400X RISC MICROPROCESSOR HUFADDR0 Description Huff_addr0 [31:0] Source or destination JPEG file address 0 HUFADDR1 Register Address Description Reset Value HUFADDR1 0x7880100C Source or destination JPEG file address 1 0x0000_0000 HUFADDR1 Description Huff_addr1 [31:0] Source or destination JPEG file address 1 HUFADDR0 and HUFADDR1 are the start address for JPEG data.
Page 762 0: Don’t start main decoding process. 1: Start main decoding process. JPEG Decoding Process in S3C6400X S_JSTART command initiate JPEG decoding process and if JPEG engine get header information of JPEG file, (this mean high HD_IRQ value are detected) S_JRSTART command is set high to start main decoding process.
Page 763 JPEG CODEC S3C6400X RISC MICROPROCESSOR COEF1 Register Address Description Reset Value COEF1 0x78801020 Coefficient values for RGB ↔ YCbCr converter 0x0000_0000 COEF1 Description Reserved [31:24] Reserved COEF11 [23:16] Coefficient value of COEF11 Reserved [15:8] Reserved COEF13 [7:0] Coefficient value of COEF13...
Page 764 S3C6400X RISC MICROPROCESSOR JPEG CODEC Reserved [7:0] Reserved The calculation in YCbCr converter is based on the following matrix. YCbCr converter is used when SWSEL = 0x2 (RGB565) on encode mode. COEF11 COEF13 Y - c1 COEF21 COEF22 COEF23 Cb - 128...
Page 765 JPEG CODEC S3C6400X RISC MICROPROCESSOR JPEG unit waits until the input next_partial_lines signal is set to high. Setting the signal high, makes the JPEG unit decodes the next 8 or 16 lines of the decoded image. This process repeats until the decoding is completed.
Page 766 This specification defines the interface between the Base-band Modem (MSM) and the Application Processor for the data-exchange of these two devices (refer Figure 23-1). For the data-exchange, the AP (Application Processor, S3C6400X) has a dual-ported SRAM buffer (on-chip) and the Modem chip can access that SRAM buffer using a typical asynchronous-SRAM interface.
Page 767 S3C6400X MODEM INTERFACE RISC MICROPROCESSOR Features MSM Interface Features Asynchronous SRAM interface style interface 16-bit parallel bus for data transfer 8K bytes internal dual-port SRAM buffer Interrupt request for data exchange Programmable interrupt port address Memory Map Register Address Description...
Page 768 AP clears the interrupt clear registers by writing any value to the registers. Modem chip or AP(S3C6400X) can read the data that indicates what event happens – data transfer requested, data transfer done, special command issued, etc. - from interrupt port address. That data format should be defined for communication between the modem chip and AP.
Page 769 S3C6400X MODEM INTERFACE RISC MICROPROCESSOR AP Booting for MODEM AP Booting for MODEM means that AP provides the boot area (8Kbyte memory) for MODEM. MODEM can boot using internal Dual-Port SRAM memory inside MODEM_IF block. In this case, AP should provide ‘MODEM Reset pin’...
Page 770 S3C6400X RISC MICROPROCESSOR MODEM INTERFACE Modem I/F Indirect Modem I/F External Modem Direct Modem I/F SYSCON 8KByte DPRAM NFCON Stepping Stone GPIO (1) AP write boot pgm to DPRAM (read from NAND) (2) AP release BB reset (3) BB read boot pgrm from Direct modem I/F...
Page 771: Address Mapping
S3C6400X MODEM INTERFACE RISC MICROPROCESSOR Address mapping Dual Port SRAM Address map Modem (half-word) Buffer of S3C6400X (word ) (word) XhiADR [12:0] 0x000 0x74100000 0x000 0x000 0x001 0x004 0x74100004 0x002 0x002 0x008 0x74100008 0x004 8K Bytes 0x003 0x00C 0x7410000C 0x006...
Page 772 S3C6400X RISC MICROPROCESSOR MODEM INTERFACE When XhiCSn = ‘0’, Address mapping of the Modem Side is following XhiADDR Host/Modem Interface select description [12] [11:8] Modem Interface (Direct interface) Xhi_ADDR[2]='0' : Indirect Host I/F, 0000 Host Interface (Indirect interface) Xhi_ADDR[2]='1' : MDPIF...
Page 773 S3C6400X MODEM INTERFACE RISC MICROPROCESSOR Timing Diagram AVWR XhiADR CSVWR XhiCSn XhiWEn DSUWR DHWR XhiDATA Figure 23-5 Modem interface write timing diagram Table 23-2 Modem interface write timing Parameter Description Min (ns) Max (ns) Notes Address valid to address invalid...
Page 774 S3C6400X RISC MICROPROCESSOR MODEM INTERFACE AVRD XhiADR CSVRD XhiCSn CSRD XhiOEn RDDV XhiDATA ACSDV Figure 23-6 Modem interface read timing diagram Table 23-3 Modem interface read timing Parameter Description Min (ns) Max (ns) Notes Address valid to address invalid 50 ns...
Page 775 S3C6400X MODEM INTERFACE RISC MICROPROCESSOR Software Interface and Registers This modem interface provides a generic data-exchange method. This interface does not implement any other complex features except for the interrupt-request/clear such as automatic FIFO managements, etc. The software should be responsible for all other required functionalities for the data exchange between the modem chip and the AP such as the data exchange protocol, the data buffer managements, and etc.
Page 776 S3C6400X RISC MICROPROCESSOR MODEM INTERFACE Modem Interface Control Register (MIFCON) Register Address Description Reset Value MIFCON 0x74108008 Modem Interface Control register 0x00000008 MIFCON Description Initial State Reserved [31:4] Interrupt to MSM(Modem) Enable INT2MSMEN : MSM_nIRQ is interrupt signal enable. ‘0’=Disable, ‘1’=Enable...
Page 777 [31:0] pending register of MSM modem interface. Note. The interrupt controllers of AP(S3C6400X), VIC, receive level-triggered type interrupt requests. Therefore, interrupt requests from MODEM_IF block are maintained until ARM(the interrupt service routine S/W) clears this register by writing to HIGH.
Page 778: Host Interface
HOST INTERFACE HOST INTERFACE Overview The Host Interface block in the S3C6400X supports indirect access of the external host device (Ex: Modem Chip). By the selected host interface protocol, the following operations are supported: Read of a 16-bit protocol register...
Page 779 S3C6400X HOST INTERFACE RISC MICROPROCESSOR AP(S3C6400) LCD Bypass : CPU I/F To LCD out MODEM_IF Decoder External Modem MODEM IF Address (Direct Modem I/F) Decoding HOST IF (Indirect Host I/F, CPUIF_CLIENT) MDP I/F Figure 24-2 Data flow of the the External Host device (MODEM) and the AP The External Host Interface of the AP supports (a) the Direct Modem Interface path (MODEM_IF), (b) Indirect Modem Interface path (HOST_IF), (c) MDP Interface path (MDP_IF) and (d) the LCD bypass path.
Page 780 S3C6400X RISC MICROPROCESSOR HOST INTERFACE When XhiCSn = ‘0’, Address mapping of the Modem Side is following XhiADDR Host/Modem Interface select description [12] [11:8] Modem Interface (Direct interface) Xhi_ADDR[2]='0' : Indirect Host I/F, 0000 Host Interface (Indirect interface) Xhi_ADDR[2]='1' : MDPIF...
Page 781 S3C6400X HOST INTERFACE RISC MICROPROCESSOR Features Host Interface (Indirect Modem Interface) Features Asynchronous indirect 16-bit SRAM-style host interface (i80) Banked 16-bit protocol registers for host interface Write-FIFO and Read-FIFO to support burst write/read transfer up to 1 Kbytes A 32-bit in-mailbox register and a 32-bit out-mailbox register for data exchange...
Page 782 S3C6400X RISC MICROPROCESSOR HOST INTERFACE Read and Write of a 16-bit Protocol Register To access a 16-bit protocol register take the following steps: First select a corresponding bank by writing BSEL, then Read or write the protocol register. Read and Write of Two 16-bit Protocol Registers in the Same Bank...
Page 783 S3C6400X HOST INTERFACE RISC MICROPROCESSOR Single Read Figure 24-5. Single Read Procedure The name “CPUIF Client” means HOST Interface block and the name “CPU” means External Host device (ex. MODEM) in this section. The CPUIF Client reads a result from AP (S3C6400) and it can start a new read operation before the completion of the previous one.
Page 784 S3C6400X RISC MICROPROCESSOR HOST INTERFACE Burst Write Change Bank (BSEL Select Bank 0) STAT[15:8] < (BLEN + 3) / 2 Read STAT CTRL RW= Write , BLEN>1 Change Bank (BSEL Select Bank 8) hDATA a 32-bit address BLEN times hDATA...
Page 785 S3C6400X HOST INTERFACE RISC MICROPROCESSOR Repeated Burst Write to reduce the HOST CPU (ex. Modem) overhead Figure 24-8. Repeated Burst Write Procedure With ‘Repeated Burst Write’ and DMA, a large data of MP (Modem Processor) can be transferred to a “Destination area”.
Page 786 S3C6400X RISC MICROPROCESSOR HOST INTERFACE MODEM Booting MODEM Booting means that the Host(Modem) controls AP booting including Reset. In this case, AP does not need to have External Boot Memory(NAND). Modem download the AP boot code from its Boot Memory to the Stepping Stone memory area(4Kbyte) inside AP through HOST I/F(indirect modem I/F) block.
Page 787 S3C6400X HOST INTERFACE RISC MICROPROCESSOR Modem I/F Indirect Modem I/F External Modem Direct Modem I/F SYSCON 8KByte DPRAM NFCON Reset Stepping Stone GPIO WakeUp (1) Modem release AP Reset : All system except ARM and WDT go to normal state (2) Modem write booting code to S.S.
Page 788 S3C6400X RISC MICROPROCESSOR HOST INTERFACE Mailbox Interface The modem can use a 32-bit in-mailbox and a 32-bit out-mailbox for IPC (Inter Process Communication) between the modem and the AP (S3C6400). Mailbox basic operation When the modem writes a 32-bit data into the in-mailbox, the CPUIF Client generates an interrupt to the AP (S3C6400)’s CPU so that the AP (S3C6400)’s CPU will read the in-mailbox to know the requests from the...
Page 789 S3C6400X HOST INTERFACE RISC MICROPROCESSOR Mailbox operation with a bulk data When a 32-bit mailbox is not enough to transfer information, any memory of AP(S3C6400) can be used as buffer memory. For example, in order to transfer a bulk data from the host to AP(S3C6400), the host first writes the data into a memory in AP(S3C6400) by using Burst Write of the CPUIF Client.
Page 790 S3C6400X RISC MICROPROCESSOR HOST INTERFACE Programmer’s Model The registers of HOST Interface are classified into: Protocol Registers that are accessed through 16-bit Host Interface by modem, and Special Function Registers that are accessed through SYSTEM bus by the bus master.
Page 791 S3C6400X HOST INTERFACE RISC MICROPROCESSOR Register Descriptions (Protocol Registers) Register Bank MP_A[1:0] Description Reset Value CTRL Control Register 0x0000 INTE Interrupt Enable Register 0x2000 STAT Status Register 0x90A2 CTRL1 Control1 Register 0x0000 INTE1 Interrupt Enable1 Register 0x0000 STAT1 Status1 Register...
Page 792 S3C6400X RISC MICROPROCESSOR HOST INTERFACE Protocol Register Matrix As shown in Table 24-2 and Table 24-3, protocol registers are classed into 16 banks so that BSEL[3:0] must be properly set before access. Table 24-2 Protocol Register Matrix (Bank0 ~ Bank7)
Page 793 S3C6400X HOST INTERFACE RISC MICROPROCESSOR Control Register (CTRL) BSEL[3:0] = 0000, MP_A[1:0] = 00, R/W, Reset value = 0x0000 Field Description Initial State Reserved [15:13] BLEN[8:0] [12:4] Burst length for transfer 0_0000_0000 The basic unit is a 32-bit word. Maximum burst length is 256 words.
Page 794 S3C6400X RISC MICROPROCESSOR HOST INTERFACE Status Register (STAT) BSEL [3:0] = 0000, MP_A[1:0] = 10, R, Reset value = 0x90A2 Field Description Initial State WRITABLE_CNT [15:8] Writable word counts in wfifo: Read only 0x90 This field shows how many words can be written into WFIFO without checking of the WFIFO fullness.
Page 795 S3C6400X HOST INTERFACE RISC MICROPROCESSOR Control1 Register (CTRL1) BSEL[3:0] = 0001, MP_A[1:0] = 00, R/W, Reset value = 0x0000 Field Description Initial State Reserved [15:4] 0x000 Reserved [3:2] DAMT [1:0] CPUIF Hold Margin Delay Amount In order to gurantee the hold timing, address and data signals are delayed.
Page 796 S3C6400X RISC MICROPROCESSOR HOST INTERFACE In-Mail Box Low Register (IMBL) BSEL[3:0] = 0010, MP_A[1:0] = 00, R/W, Reset value = 0x0000 Field Description Initial State IMBL [15:0] Lower 16 bits of In-Mail Box register 0x0000 CPU writes a 16-bit data into IMBL.
Page 797 S3C6400X HOST INTERFACE RISC MICROPROCESSOR Host Interface Data Low Register (hDATAL) BSEL[3:0] = 1000, MP_A[1:0] = 00, R/W, Reset value = (undefined) Field Description Initial State DATAL [15:0] Data Register Host Interface Data High Register (hDATAH) BSEL[3:0] = 1000, MP_A[1:0] = 01, R/W, Reset value = (undefined)
Page 798 S3C6400X RISC MICROPROCESSOR HOST INTERFACE Register Descriptions (Special Function Registers) Base address : 0x7400_0000 Register Offset Description Reset Value CPUIFC_CTRL 0x000 CPUIF Client Control Register 0x20FF_0100 0x004 Reserved 0x0000_0006 Reserved CPUIFC_TMP 0x008 CPUIF Client Temporary Register 0x0000_0000 Reserved 0x00C Reserved...
Page 799 S3C6400X HOST INTERFACE RISC MICROPROCESSOR CPUIF CLIENT CONTROL REGISTER (CPUIFC_CTRL) Offset=0x00, R/W, Reset Value=0x20FF_0100 Field Description Initial State Reserved [31:30] Reserved INV_INTR [29] Polarity inversion of INTR 0: INTR is active high so that INTR becomes HIGH when an interrupt occurs.
Page 800 S3C6400X RISC MICROPROCESSOR HOST INTERFACE CPUIF Status Mirrored Register (CPUIFC_MR_STAT) Offset=0x20, R/W, Reset Value=0x0000_90A2 Field Description Initial State Reserved [31:16] Reserved 0x0000 STAT [15:0] Mirrored Protocol Register of STAT[15:0] 0x90A2 CPUIF Status1 Mirrored Register (CPUIFC_MR_STAT1) Offset=0x24, R/W, Reset Value=0x0000_0002 Field...
Page 801 S3C6400X HOST INTERFACE RISC MICROPROCESSOR CPUIF Status2 Register (CPUIFC_STAT2) Offset=0x28, R/W, Reset Value=0x0001_0000 Field Description Initial State Reserved Reserved 0x000 [31:20] Reserved Reserved [19] RBURST_DONE Repeated burst write done flag [18] This flag is set when the repeated burst write is done. In order to clear the flag, write HIGH value.
Page 802 S3C6400X RISC MICROPROCESSOR HOST INTERFACE Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 24-25 Specifications and information herein are subject to change without notice.
Page 803 S3C6400X HOST INTERFACE RISC MICROPROCESSOR CPUIF Interrupt Enable Mirrored Register (CPUIFC_MR_INTE) Offset=0x30, R/W, Reset Value=0x0000_2000 Field Description Initial State Reserved [31:16] 0x0000 INTE [15:0] Mirrored Protocol Register of INTE[15:0] 0x2000 CPUIF Interrupt Enable1 Mirrored Register (CPUIFC_MR_INTE1) Offset=0x34, R/W, Reset Value=0x0000_0000...
Page 804 S3C6400X RISC MICROPROCESSOR HOST INTERFACE Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 24-27 Specifications and information herein are subject to change without notice.
Page 805 USB HOST CONTROLLER USB HOST CONTROLLER This chapter describes the Universal Serial Bus host controller (USB) implemented in S3C6400 RISC microprocessor. OVERVIEW S3C6400X supports 2-port USB host interface as follows: • OHCI Rev 1.0 compatible • USB Rev1.1 compatible •...
Page 806 USB HOST CONTROLLER S3C6400X USB HOST CONTROLLER SPECIAL REGISTERS The S3C6400X USB host controller complies with OHCI Rev 1.0. Refer to Open Host Controller Interface Rev 1.0 specification for detailed information. Table 25-1. OHCI Registers for USB Host Controller Register...
Page 807 HcPeriodicStart 0x74300040 USB Host Controller Periodic Start 0x0000_0000 Register HcLSThreshold 0x74300044 USB Host Controller Low-Speed 0x0000_0628 Threshold Register HcRhDescriptorA 0x74300048 USB Host Controller Root Hub 0x0200_1202 Descriptor A Register HcRhDescriptorB 0x7430004C USB Host Controller Root Hub 0x0000_0000 Descriptor B Register HcRhStatus 0x74300050 USB Host Controller Root Hub Status...
Page 808 USB2.0 HS OTG OVERVIEW Samsung USB On-The-Go (OTG) is a Dual-Role Device (DRD) controller, which supports both device and host functions. It is fully compliant with the On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a. It supports high-speed (HS, 480-Mbps), full-speed (FS, 12-Mbps), and low-speed (LS, 1.5-Mbps) transfers. HS OTG can be configured as a Host-only or Device-only controller.
Page 809 Registers (CSRs). The OTG Link has an AHB Master to enable the link to transfer data on the AHB. The S3C6400x USB system shown in Figure 26-1, can be configured as following: 1. USB 1.1 Host 1 Port & USB 2.0 OTG 1 Port 2.
Page 810 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG MODES OF OPERATION The application can operate the Link either in DMA mode or in Slave mode. The application cannot operate the core using DMA and Slave modes simultaneously. DMA Mode USB OTG host uses the AHB Master interface to transmit packet data fetch (AHB to USB) and receive data update (USB to AHB).
Page 811 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR REGISTER MAP OVERVIEW The OTG PHY control registers based on address 7C10_0000h must be accessed to control and observe the OTG PHY. The OTG Link Core registers based on address 7C00_0000h is classified as follows: —...
Page 812 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG OTG LINK CSR MEMORY MAP Figure 26-2 shows the OTG link CSR address map. Host and Device mode registers occupy different addresses. All registers are implemented in the AHB Clock domain. OTG LINK BASE + 0000h...
Page 813 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR APPLICATION ACCESS TO THE CSRS The Access column of each register description that follows specifies how the application and the core can access the register fields of the CSRs. The following conventions are used.
Page 814 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG HS OTG CONTROLLER SPECIAL REGISTERS Table 26-1 Register summary of HS OTG Controller Register Offset Description Reset Value OTG PHY CONTROL REGISTERS (Base address : 0x7C10_0000) OPHYPWR 0x000 OTG PHY Power Control Register 0x0000_000F...
Page 815 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR Host Mode Registers Host Global Registers HCFG 0x400 Host Configuration Register 0x0020_0000 HFNUM 0x408 Host Frame Number/Frame Time Remaining 0x0000_0000 Register HPTXSTS 0x410 Host Periodic Transmit FIFO/Queue Status 0x0008_1800 Register HAINT 0x414 Host All Channels Interrupt Register...
Page 816 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG HCINT4 0x588 Host Channel 4 Interrupt Register 0x0000_0000 HCINTMSK4 0x58C Host Channel 4 Interrupt Mask Register 0x0000_0000 HCTSIZ4 0x580 Host Channel 4 Transfer Size Register 0x0000_0000 HCDMA4 0x584 Host Channel 4 DMA Address Register...
Page 817 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR HCTSIZ10 0x650 Host Channel 10 Transfer Size Register 0x0000_0000 HCDMA10 0x654 Host Channel 10 DMA Address Register 0x0000_0000 HCCHAR11 0x660 Host Channel 11 Characteristics Register 0x0000_0000 HCSPLT11 0x664 Host Channel 11 Spilt Control Register...
Page 818 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG Register DOEPMSK 0x814 Device OUT Endpoint Common Interrupt Mask 0x0000_0000 Register DAINT 0x818 Device ALL Endpoints Interrupt Register 0x0000_0000 DAINTMSK 0x81C Device ALL Endpoints Interrupt Mask Register 0x0000_0000 DTKNQR1 0x820 Device IN Token Sequence Learning Queue Read...
Page 819 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR DIEPDMA5 0x9B4 Device IN Endpoint 5 DMA Address Register 0x0000_0000 DIEPCTL6 0x9C0 Device Control IN Endpoint 6 Control Register 0x0000_0000 DIEPINT6 0x9C8 Device IN Endpoint 6 Interrupt Register 0x0000_0000 DIEPTSIZ6 0x9D0 Device IN Endpoint 6 Transfer Size Register...
Page 820 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG DIEPINT15 0xAE8 Device IN Endpoint 15 Interrupt Register 0x0000_0000 DIEPTSIZ15 0xAF0 Device IN Endpoint 15 Transfer Size Register 0x0000_0000 DIEPDMA15 0xAF4 Device IN Endpoint 15 DMA Address Register 0x0000_0000 Device Logical OUT Endpoint-Specific Registers...
Page 821 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR DOEPTSIZ8 0xC10 Device OUT Endpoint 8 Transfer Size Register 0x0000_0000 DOEPDMA8 0xC14 Device OUT Endpoint 8 DMA Address Register 0x0000_0000 DOEPCTL9 0xC20 Device Control OUT Endpoint 9 Control Register 0x0000_0000 DOEPINT9 0xC28 Device OUT Endpoint 9 Interrupt Register...
Page 822 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG OTG PHY CONTROL REGISTERS OTG PHY POWER CONTROL REGISTER (OPHYPWR) Register Address Description Reset Value OPHYPWR 0x7C10_0000 OTG PHY Power Control Register 32 bits OPHYPWR Description Initial State [31:4] Reserved 28’h0 analog_powerdown Analog block power down in PHY2.0 1’b1...
Page 823 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR OTG PHY CLOCK CONTROL REGISTER (OPHYCLK) Register Address Description Reset Value OPHYCLK 0x7C10_0004 OTG PHY Control Register 32 bits OPHYCLK Description Initial State [31:7] Reserved 25’h0 serial_mode UTMI/Serial Interface Select 1’b0 When this register is asserted, USB traffic flows through the serial interface.
Page 824 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG Figure 26-3. OTG PHY Clock Path OTG RESET CONTROL REGISTER (ORSTCON) Register Address Description Reset Value ORSTCON 0x7C10_0008 OTG Reset Control Register 32 bits ORSTCON Description Initial State [31:3] Reserved 29’h0 phylnk_sw_rst OTG Link Core phy_clock domain S/W Reset 1’b0...
Page 825 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR OTG LINK CORE REGISTERS OTG GLOBAL REGISTERS These registers are available in both Host and Device modes, and not required to be reprogrammed when switching between these modes. OTG CONTROL AND STATUS REGISTER (GOTGCTL) The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.
Page 826 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG · 1’b1 : HNP is enabled in the application HstSetHNPEn [10] Host Set HNP Enable 1’b0 The application sets this bit when it has successfully enabled HNP on the connected device. · 1’b0 : Host Set HNP is not enabled ·...
Page 827 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR DbnceDone [19] R_SS_ Debounce Done 1’b0 The core sets this bit when the debounce is completed after the device connects. This bit is only valid when the HNP Capable or SRP Capable bit is set in the Core USB Configuration register.
Page 828 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG the Periodic TxFIFO is half empty · 1’b1 : GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty NPTxFEmpLvl Non-Periodic TxFIFO Empty Level 1’b0 Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINSTS.NPTxFEmp) is triggered.
Page 829 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR GUSBCFG Description Initial State [31:16] Reserved 16’h0 PHY Low-Power [15] PHY Low-Power Clock Select 1’b0 Clock Select Selects either 480-MHz or 48-MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48-MHz clock to save power.
Page 830 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG AHBIdle [31] AHB Master Idle 1’b1 Indicates that the AHB Master State Machine is in the IDLE condition. DMAReq [30] DMA Request Signal 1’b1 Indicates that the DMA request is in progress. Used for debug.
Page 831 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR HSftRst R_WS_ HClk Soft Reset 1’b0 The application uses this bit to flush the control logic in the AHB Clock domain. Only AHB Clock Domain pipelines are reset. · FIFOs are not flushed with this bit.
Page 832 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG reset for proper operation. CORE INTERRUPT REGISTER (GINTSTS) This register interrupts the application for system-level events in the current mode of operation (Device mode or Host mode). Register Address Description Reset Value GINTSTS 0x7C00_0014...
Page 833 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR The core sets this bit to indicate a change in port status of one of the OTG core ports in Host mode. The application must read the Host Port Control and Status (HPRT) register to determine the exact event that caused this interrupt.
Page 834 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG incomplSOIN [20] R_SS_ Incomplete Isochronous IN Transfer 1’b0 The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current microframe.
Page 835 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR the Device Status (DSTS) register to obtain the enumerated speed. USBRst [12] R_SS_ USB Reset 1’b0 The core sets this bit to indicate that a reset is detected on the USB. USBSusp [11] R_SS_ USB Suspend 1’b0...
Page 836 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG R_SS_ Start of (micro) Frame 1’b0 In Host mode, the core sets this bit to indicate that an SOF (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt.
Page 837 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR ConIDStsChngMsk [28] Connector ID Status Change Mask 1’b0 [27] Reserved 1’b0 PTxFEmpMsk [26] Periodic TxFIFO Empty Mask 1’b0 HChIntMsk [25] Host Channels Interrupt Mask 1’b0 PrtIntMsk [24] Host Port Interrupt Mask 1’b0 [23] Reserved 1’b0...
Page 838 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG receive status pop/read when the receive FIFO is empty and returns a value of 32’h0000_0000. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted.
Page 839 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR GRXSTSR/ Description Initial State GRXSTSP [31:25] Reserved 7’h0 [24:21] Frame Number 4’h0 This is the least significant 4 bits of the (micro)frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported.
Page 840 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG · Maximum value is 32768 The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth (6144). A new value must be written to this field. Programmed values must not exceed the power-on value set.
Page 841 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR [31] Reserved 1’b0 NPTxQTop [30:24] Top of the Non-Periodic Transmit Request Queue 7’h0 Entry in the Non-Periodic Tx Request Queue that is currently being processed by the MAC. · Bits[30:27] : Channel/endpoint number · Bits[26:25] : ·...
Page 842 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG The power-on reset value of this register is specified as the Largest Host Mode Periodic Tx Data FIFO Depth (6144). A new value must be written to this field. Programmed values must not exceed the power-on value set.
Page 843 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR DPTxFStAddr [15:0] Device Periodic TxFIFO RAM Start Address n :1 (16’h3000) Holds the start address in the RAM for this periodic n :2 (16’h3300) FIFO. n :3 (16’h3600) The power-on reset value of this register is sum of the Largest Rx Data FIFO Depth, Largest Non- n :4 (16’h3900)
Page 844 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG make changes to this field after initial programming. · 1’b0 : HS/FS/LS, based on the maximum speed supported by the connected device · 1’b1 : FS/LS -only, even if the connected device can support HS...
Page 845 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR Register Address Description Reset Value HPTXSTS 0x7C00_0410 Host Periodic Transmit FIFO/Queue Status Register 32 bits HPTXSTS Description Initial State PTxQTop [31:24] Top of the Periodic Transmit Request Queue 8’h0 This indicates the entry in the Periodic Tx Request Queue that is currently being processes by the MAC.
Page 846 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG HAINT Description Initial State [31:16] Reserved 16’h0 HAINT [15:0] Channel Interrupts 16’h0 One bit per channel : Bit 0 for Channel 0, bit 15 for Channel 15 HOST ALL CHANNELS INTERRUPT MASK REGISTER (HAINTMSK) The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the application when an event occurs on a channel.
Page 847 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR · 2’b01 : Full speed · 2’b10 : Low speed · 2’b11 : Reserved PrtTstCtl [16:13] Port Test Control 4’h0 The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port.
Page 848 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG application sets the Port Reset bit or Port Resume bit in this register or the Resume/Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit in the Core Interrupt register. · 1’b0 : Port not in Suspend mode ·...
Page 849 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR HOST CHANNEL-SPECIFIC REGISTERS HOST CHANNEL-n CHARACTERISTICS REGISTER (HCCHARn) Channel_number: 0≤ n≤ 15 Register Address Description Reset Value HCCHARn 0x7C00_0500 Host Channel-n Characteristics Register 32 bits +n*20h HCCHARn Description Initial State ChEna [31] R_WS_ Channel Enable 1’b0...
Page 850 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG This field must be set to at least 2’b01. EPType [19:18] Endpoint Type 2’b0 Indicates the transfer type selected. · 2’b00 : Control · 2’b01 : Isochronous · 2’b10 : Bulk · 2’b11 : Interrupt...
Page 851 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR transaction. · 2’b00 : Mid. This is the middle payload of this transaction. · 2’b01 : End. This is the last payload of this transaction. HubAddr [13:7] Hub Address 7’h0 This field holds the device address of the transaction translator’s hub.
Page 852 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel’s DMA address register to get the error address. ChHltd R_SS_ Channel Halted 1’b0...
Page 853 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR HCTSIZn Description Initial State DoPng [31] Do Ping 1’h0 Setting this field to 1 directs the host to do PING protocol. [30:29] 2’b0 The application programs this field with the type of PID to use for the initial transaction. The host will maintain this field for the rest of the transfer.
Page 854 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG DEVICE MODE REGISTERS These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. Some of them affect all the endpoints uniformly, while others affect only a specific endpoint. Device Mode registers fall into two categories: ·...
Page 855 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR control transfer’s Status stage. · 1’b0 : Send a STALL handshake on a nonzero- length status OUT transaction and do not send the received OUT packet to the application. · 1’b1 : Send the received OUT packet to the...
Page 856 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG NAK. SGNPInNAK Set Global Non-Periodic IN NAK 1’b0 A write to this field sets the Global Non-Periodic IN NAK. The application uses this bit to send a NAK handshake on all non-periodic IN endpoints. The core can also set this bit when a timeout condition is detected on a non-periodic endpoint.
Page 857 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1- 15ms after setting it.
Page 858 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG asserted due to an erratic error, the application can only perform a soft disconnect recover. EnumSpd [2:1] Enumerated Speed 2’h0 Indicates the speed at which the OTG core has come up after speed detection through a chirp sequence.
Page 859 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR DEVICE OUT ENDPOINT COMMON INTERRUPT MASK REGISTER (DOEPMSK) This register works with each of the Device OUT Endpoint Interrupt registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupts for a specific status in the DOEPINTn register can be masked by writing to the corresponding bit in this register.
Page 860 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG Bit 0 for IN endpoint 0, bit 15 for endpoint 15 DEVICE ALL ENDPOINTS INTERRUPT MASK REGISTER (DAINTMSK) The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the application when an event occurs on a device endpoint.
Page 861 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR [6:5] Reserved 2’h0 INTKnWPtr [4:0] IN Token QUEUE Write Pointer 5’h0 DEVICE IN TOKEN SEQUENCE LEARNING QUEUE READ REGISTER 2 (DTKNQR2) Read from this register returns the next 8 endpoint entries of the learning queue.
Page 862 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG DEVICE IN TOKEN SEQUENCE LEARNING QUEUE READ REGISTER 4 (DTKNQR4) Read from this register returns the next 8 endpoint entries of the learning queue. Register Address Description Reset Value DTKNQR4 0x7C00_0834 Device IN Token Sequence Learning Queue Read...
Page 863 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR value equals : Vbus pulse time in PHY clocks /1,024 DEVICE LOGICAL ENDPOINT-SPECIFIC REGISTERS A logical endpoint is unidirectional: it can be either IN or OUT. To represent a bidirectional endpoint, two logical endpoints are required, one for the IN direction and the other for the OUT direction. This is also true for control endpoints.
Page 864 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG Periodic Transmit FIFO. Stall [21] R_WS_ STALL Handshake 1’b0 The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority.
Page 865 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR Register Address Description Reset Value DOEPCTL0 0x7C00_0B00 Device Control OUT Endpoint 0 Control Register 32 bits DOEPCTL0 Description Initial State EPEna [31] R_WS_ Endpoint Enable 1’b0 Indicates that the application has allocated the memory to start receiving data from the USB. The core clears this bit before setting any of the following interrupts on this endpoint.
Page 866 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG · 1’b0: The core is transmitting non-NAK handshakes based on the FIFO status · 1’b1: The core is transmitting NAK handshakes on this endpoint When either the application or the core sets this bit, the core stops receiving data, even if there is space in the RxFIFO to accommodate the incoming packet.
Page 867 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR the following interrupts on this endpoint : · SETUP Phase Done (OUT only) · Endpoint Disabled · Transfer Complete Transfer Completed Note : For control OUT endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Page 868 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG Periodic endpoints must map this to the corresponding Periodic TxFIFO number. · 4’h0 : Non-Periodic TxFIFO · Others : Specified Periodic TxFIFO number Note: An interrupt IN endpoint could be configured as a non-periodic endpoint for applications like mass storage.
Page 869 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR transmitting any data on an IN endpoint, even if there data is available in the TxFIFO. · For isochronous IN endpoints : The core sends out a zero-length data packet, even if there data is available in the TxFIFO.
Page 870 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG DEVICE ENDPOINT-n INTERRUPT REGISTER (DIEPINTn/DOEPINTn) Endpoint_number : 0≤ n≤ 15 This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register is set.
Page 871 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR For OUT endpoints, this bit is reserved. INTknTXFEmp R_SS_ IN Token Received When TxFIFO is Empty 1’b0 Applies to non-periodic IN endpoints only. Indicates that an IN token was received when the associated TxFIFO was empty. This interrupt is asserted on the endpoint for which the IN token was received.
Page 872 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG Register Address Description Reset Value DIEPTSIZ0 0x7C00_0910 Device IN Endpoint 0 Transfer Size Register 32 bits DIEPTSIZ0 Description Initial State [31:20] Reserved 12’h0 PktCnt [19] Packet Count 1’b0 Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.
Page 873 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from RxFIFO and written to the external memory.
Page 874 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG · 2’b10 : DATA2 · 2’b11 : MDATA SUPCnt SETUP Packet Count Applies to control OUT Endpoints only. This field specifies the number of back-to-back SETUP data packets the endpoint can receive. · 2’b01: 1 packet ·...
Page 875 USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR DIEPDMAn/ Description Initial State DOEPDMAn DMAAddr [31:0] DMA Address 32’h0 Holds the start address of the external memory for storing or fetching endpoint data. This register is incremented on every AHB transaction. Note: For control endpoints, this address stores control OUT data packets as well as SETUP transaction data packets.
Page 876 S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG NOTE Preliminary product information describe products that are in development, 26-69 for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 877 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER HIGH-SPEED MMC CONTROLLER This chapter describes the MultiMediaCard controller and related registers supported by S3C6400X RISC microprocessor. OVERVIEW The HSMMC (High-speed MMC) SDMMC is a combo host for Secure Digital card and MultiMediaCard. This host is compatible for SD Association’s (SDA) Host Standard Specification.
Page 878 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR BLOCK DIAGRAM HCLK SDCLK Domain Domain BaseCLK Status Clock Control INTREQ Status CMDRSP System packet (AHB) Line Control Control Control FIFO AHB slave I/F Control Control DPSRAM Status controller DATA AHB master packet Figure 27-1. HSMMC block diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 879 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER SEQUENCE This section defines basic sequence flow chart divided into several sub sequences. “ Wait for interrupts” is used in the flow chart. This means the Host Driver waits until specified interrupts are asserted. If already asserted, then follow the next step in the flow chart.
Page 880 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR (3) Check Card Inserted in the Present State register. In this case where Card Inserted is 1, the Host Driver can supply the power and the clock to the SD card. In this case where Card Inserted is 0, the other executing processes of the Host Driver shall be immediately closed.
Page 881 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER SD CLOCK STOP SEQUENCE START Set SD Clock OFF Stop SD Clock Figure 27-4. SD Clock Stop Sequence The flow chart for stopping the SD Clock is shown in Figure 27-4. The Host Driver does not stop the SD Clock when a SD transaction takes place on the SD Bus -- namely, when either Command Inhibit (DAT) or Command Inhibit (CMD) in the Present State register is set to 1.
Page 882 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR SD BUS POWER CONTROL SEQUENCE START Get the support voltage of the Host Controller Set SD Bus voltage select with supported maximum voltage Set SD Bus Power Get OCR value of the SD Card no change...
Page 883 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER (5) Judge whether SD Bus voltage must be changed or not. If SD Bus voltage must be changed, go to step (6). If SD Bus voltage does not to be changed, go to ‘End’. (6) Set SD Bus Power in the Power Control register to 0 for clearing this bit. The card requires voltage rising from 0 volt to detect it correctly.
Page 884 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR (4) Change the bit mode for a SD card. Change SD memory card bus width by ACMD6 and SDIO card bus width by setting Bus Width of Bus Interface Control register in CCCR. (5) In case of you want to change to 4-bit mode, set Data Transfer Width in the Host Control register to 1. In another case (1-bit mode), set this bit to 0.
Page 885 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER In this specification the first and the second case’s transactions are classified as “Transaction Control without Data Transfer using DAT Line”, the third case’s transaction is classified as “Transaction Control with Data Transfer using DAT Line”.
Page 886 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR SD COMMAND ISSUE SEQUENCE Figure 27-9. Timeout Setting Sequence Take the following steps for Timeout Setting: (1) Check Command Inhibit (CMD) in the Present State register. Repeat this step until Command Inhibit (CMD) is 0. That is, when Command Inhibit (CMD) is 1, the Host Driver will not issue a SD Command.
Page 887 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER (4) Check Command Inhibit (DAT) in the Present State register. Repeat this step until Command Inhibit (DAT) is (5) Set the value corresponding to the issued command in the Argument register. (6) Set the value corresponding to the issued command in the Command register.
Page 888 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR START Wait for Command Complete Int Command Complete Int occur Clr Command Complete Status Get Response Data Command with Transfer Complete Int ? Wait for Transfer Complete Int Transfer Complete Int occur Clr Transfer Complete Status...
Page 889 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER TRANSACTION CONTROL WITH DATA TRANSFER USING DAT LINE Depending on whether DMA (optional) is used or not, there are two execution methods. The sequence not using DMA is shown in Figure 27-11 and the sequence using DMA is shown in Figure 27-12.
Page 890 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR Not Using DMA START Set Block Size Reg Set Command Reg Wait for Command Set Block Count Reg Complete Int Command Complete Int occur Set Argument Reg Clr Command Complete Status Set Transfer Mode Reg...
Page 891 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER (1) Set the value corresponding to the executed data byte length of one block to Block Size register. (2) Set the value corresponding to the executed data block count to Block Count register. (3) Set the value corresponding to the issued command to Argument register.
Page 892 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR Using DMA START Set System Address Reg (10) Set Block Size Reg Wait for Transfer Complete Int and DMA Int Set Block Count Reg Transfer Complete Int (11) occur Check Interrupt Status Set Argument Reg...
Page 893 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER Note: When writing to the upper byte of the Command register, the SD command is issued and DMA is started. (7) Wait for the Command Complete Interrupt. (8) Write 1 to the Command Complete in the Normal Interrupt Status register to clear this bit.
Page 894 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR ABORT TRANSACTION Abort transaction is performed by issuing CMD12 for a SD memory card and by issuing CMD52 for a SDIO card. There are two cases where the Host Driver needs to do an Abort Transaction. The first case is when the Host Driver stops Infinite Block Transfers.
Page 895 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER SDI SPECIAL REGISTERS CONFIGURATION REGISTER TYPES Configuration register fields are assigned for one of the attributes described below: Register Description Attribute Read-only register: Register bits are read-only and cannot be altered by software or any reset operation.
Page 896 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR SYSTEM ADDRESS REGISTER Register Address Description Reset Value SYSAD0 0x7C200000 System Address register (Channel 0) SYSAD1 0x7C300000 System Address register (Channel 1) SYSAD2 0x7C400000 System Address register (Channel 2) This register contains the physical system memory address used for DMA transfers.
Page 897 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER BLOCK SIZE REGISTER This register is used to configure the number of bytes in a data block. Register Address Description Reset Value BLKSIZE0 0x7C200004 Host DMA Buffer Boundary and Transfer Block Size Register (Channel 0)
Page 898 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR 0003h = 3 Bytes 0002h = 2 Bytes 0001h = 1 Byte 0000h = No data transfer Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 899 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER BLOCK COUNT REGISTER This register is used to configure the number of data blocks. Register Address Description Reset Value BLKCNT0 0x7C200006 Blocks Count For Current Transfer (Channel BLKCNT1 0x7C300006 Blocks Count For Current Transfer (Channel...
Page 900 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR ARGUMENT REGISTER This register contains the SD Command Argument. Register Address Description Reset Value ARGUMENT0 0x7C200008 Command Argument Register (Channel 0) ARGUMENT1 0x7C300008 Command Argument Register (Channel 1) ARGUMENT2 0x7C400008 Command Argument Register (Channel 2)
Page 901 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER TRANSFER MODE REGISTER This register is used to control the operation of data transfers. The Host Driver shall set this register before issuing a command which transfers data (Refer to Data Present Select in the Command register), or before issuing a Resume command.
Page 902 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR Block Count Enable This bit is used to enable the Block Count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer. (Refer to the Table below ”Determination of Transfer Type”...
Page 903 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER COMMAND REGISTER This register contains the SD Command Argument. Register Address Description Reset Value CMDREG0 0x7C20000E Command Register (Channel 0) CMDREG1 0x7C30000E Command Register (Channel 1) CMDREG2 0x7C40000E Command Register (Channel 2) The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit (CMD) bit in the Present State register before writing to this register.
Page 904 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR Data Present Select This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0 for the following: (1) Commands using only CMD line (ex. CMD52).
Page 905 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER RESPONSE REGISTER This register is used to store responses from SD cards. Register Address Description Reset Value RSPREG0_0 0x7C200010 Response Register 0 (Channel 0) RSPREG1_0 0x7C200014 Response Register 1 (Channel 0) RSPREG2_0 0x7C200018 Response Register 2 (Channel 0)
Page 906 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR The Response Field indicates bit positions of “Responses” defined in the PHYSICAL LAYER SPECIFICATION Version 1.01. The Table (upper) shows that most responses with a length of 48 (R[47:0]) have 32 bits of the response data (R[39:8]) stored in the Response register at REP[31:0]. Responses of type R1b (Auto CMD12 responses) have response data bits R[39:8] stored in the Response register at REP[127:96].
Page 907 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER BUFFER DATA PORT REGISTER 32-bit data port register to access internal buffer. Register Address Description Reset Value BDATA0 0x7C200020 Buffer Data Register (Channel 0) BDATA1 0x7C300020 Buffer Data Register (Channel 1) BDATA2 0x7C400020 Buffer Data Register (Channel 2)
Page 908 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR PRESENT STATE REGISTER This register contains the SD Command Argument. Register Address Description Reset Value PRNSTS0 0x7C200024 RO/RO 0x000A0000 Present State Register (Channel 0) PRNSTS1 0x7C300024 RO/RO 0x000A0000 Present State Register (Channel 1) PRNSTS2 0x7C400024...
Page 909 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER 1 = No Card or Inserted 0 = Reset or Debouncing Card Inserted (RO) [16] This bit indicates whether a card has been inserted. The Host Controller shall debounce this signal so that the Host Driver will not need to wait for it to stabilize.
Page 910 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR 1 = Write enable 0 = Write disable Read Transfer Active (ROC) This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: (1) After the end bit of the read command.
Page 911 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER restart a read transfer. This bit can be cleared in either of the following cases: (1) When the end bit of the last data block is sent from the SD Bus to the Host Controller.
Page 912 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR Complete interrupt in the Normal Interrupt Status register. If the Host Controller cannot issue the command because of a command conflict error (Refer to Command CRC Error) or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set.
Page 913 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER Figure 27-3. Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer Figure 27-4. Timing of Command Inhibit (DAT) for the case of response with busy Figure 27-5. Timing of Command Inhibit (CMD) for the case of no response command Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 914 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR HOST CONTROL REGISTER This register contains the SD Command Argument. Register Address Description Reset Value HOSTCTL0 0x7C200028 Present State Register (Channel 0) HOSTCTL1 0x7C300028 Present State Register (Channel 1) HOSTCTL2 0x7C400028 Present State Register (Channel 2)
Page 915 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER POWER CONTROL REGISTER This register contains the SD Command Argument. Register Address Description Reset Value PWRCON0 0x7C200029 Present State Register (Channel 0) PWRCON1 0x7C300029 Present State Register (Channel 1) PWRCON2 0x7C400029 Present State Register (Channel 2)
Page 916 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR BLOCK GAP CONTROL REGISTER This register contains the SD Command Argument. Register Address Description Reset Value BLKGAP0 0x7C20002A Block Gap Control Register (Channel 0) BLKGAP1 0x7C30002A Block Gap Control Register (Channel 1) BLKGAP2 0x7C40002A Block Gap Control Register (Channel 2)
Page 917 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER gap. The Host Controller shall honour Stop At Block Gap Request for write transfers, but for read transfers it requires that the SD card support Read Wait. Therefore the Host Driver does not set this bit during read transfers unless the SD card supports Read Wait and has set Read Wait Control to 1.
Page 918 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR WAKEUP CONTROL REGISTER This register is mandatory for the Host Controller, but wakeup functionality depends on the Host Controller system hardware and software. The Host Driver maintains voltage on the SD Bus, by setting SD Bus Power to 1 in the Power Control register, when wakeup event via Card Interrupt is desired.
Page 919 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER CLOCK CONTROL REGISTER At the initialization of the Host Controller, the Host Driver sets the SDCLK Frequency Select according to the Capabilities register. Register Address Description Reset Value CLKCON0 0x7C20002C Command Register (Channel 0) CLKCON1...
Page 920 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR This bit is set to 1 when SD Clock output is stable after writing to SD Clock Enable in this register to 1. The SD Host Driver waits to issue command to start until this bit is set to 1. (ROC) ‘1’...
Page 921 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER TIMEOUT CONTROL REGISTER At the initialization of the Host Controller, the Host Driver can set the Data Timeout Counter Value according to the Capabilities register. Register Address Description Reset Value CMDREG0 0x7C20002E Timeout Control Register (Channel 0)
Page 922 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR Buffer Write Enable Read Transfer Active Write Transfer Active DAT Line Active Command Inhibit (DAT) Block Gap Control register Continue Request Stop At Block Gap Request Normal Interrupt Status register Buffer Read Ready Buffer Write Ready...
Page 923 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER NORMAL INTERRUPT STATUS REGISTER The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal Enable does not affect these reads. An interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1.
Page 924 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR ’1’ = Read Wait Interrupt Not Occurred Note: After checking response for the suspend command, release Read Wait interrupt status manually if BS = 0 StaCCS CCS Interrupt Status (RW1C) Command Complete Signal Interrupt Status bit is for CE-ATA interface mode.
Page 925 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER This status is set if the Buffer Write Enable changes from 0 to 1. Refer to the Buffer Write Enable in the Present State register. (RW1C) ‘1’ = Ready to write buffer ‘0’ = Not ready to write buffer...
Page 926 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR Relation between Transfer Complete and Data Transfer Data Timeout Meaning of the status Complete Error Interrupted by another factor Timeout occur during transfer Don’t care Data transfer complete ‘1’ = Data Transfer Complete ‘0’ = No transfer complete Command Complete This bit is set when get the end bit of the command response.
Page 927 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER ERROR INTERRUPT STATUS REGISTER Signals defined in this register can be enabled by the Error Interrupt Status Enable register, but not by the Error Interrupt Signal Enable register. The interrupt is generated when the Error Interrupt Signal Enable is enabled and at least one of the statuses is set to 1.
Page 928 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR Occurs when detecting that the end bit of a command response is 0. ‘1’ = End bit Error generated ‘0’ = No Error Command CRC Error Command CRC Error is generated in two cases. (1) If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response.
Page 929 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER NORMAL INTERRUPT STATUS ENABLE REGISTER Setting to 1 enables Interrupt Status. Register Address Description Reset Value NORINTSTSEN0 0x7C200034 Normal Interrupt Status Enable Register (Channel 0) NORINTSTSEN1 0x7C300034 Normal Interrupt Status Enable Register (Channel 1) NORINTSTSEN2...
Page 930 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR ‘0’ = Masked Buffer Read Ready Status Enable ‘1’ = Enabled ‘0’ = Masked Buffer Write Ready Status Enable ‘1’ = Enabled ‘0’ = Masked DMA Interrupt Status Enable ‘1’ = Enabled ‘0’ = Masked Block Gap Event Status Enable ‘1’...
Page 931 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER ERROR INTERRUPT STATUS ENABLE REGISTER Setting to 1 enables Error Interrupt Status. Register Address Description Reset Value ERRINTSTSEN0 0x7C200036 Error Interrupt Status Enable Register (Channel 0) ERRINTSTSEN1 0x7C300036 Error Interrupt Status Enable Register (Channel 1)
Page 932 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR NORMAL INTERRUPT SIGNAL ENABLE REGISTER This register is used to select which interrupt status is indicated to the Host System as the interrupt. These status bits all share the same1 bit interrupt line. To enable interrupt generate set any of this bit to 1.
Page 933 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER Buffer Read Ready Signal Enable ‘1’ = Enabled ‘0’ = Masked Buffer Write Ready Signal Enable ‘1’ = Enabled ‘0’ = Masked DMA Interrupt Signal Enable ‘1’ = Enabled ‘0’ = Masked Block Gap Event Signal Enable ‘1’...
Page 934 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR ERROR INTERRUPT SIGNAL ENABLE REGISTER This register is used to select which interrupt status is notified to the Host System as the interrupt. These status bits all share the same 1 bit interrupt line. To enable interrupt generate set any of this bit to 1.
Page 935 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER AUTOCMD12 ERROR STATUS REGISTER When Auto CMD12 Error Status is set, the Host Driver checks this register to identify what kind of error Auto CMD12 indicated. This register is valid only when the Auto CMD12 Error is set.
Page 936 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR The relation between Auto CMD12 CRC Error and Auto CMD12 Timeout Error is shown below. Auto CMD12 CRC Auto CMD12 Kinds of error Error Timeout Error No Error Response Timeout Error Response CRC Error CMD line conflict...
Page 937 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER CAPABILITIES REGISTER This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer to Software Reset For All in the Software Reset register for loading from flash memory and completion timing control.
Page 938 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR [15:14] Reserved Base Clock Frequency For SD Clock (HWInit) This value indicates the base (maximum) clock frequency for the SD Clock. Unit values are 1MHz. If the real frequency is 16.5MHz, the lager value is set to 01 0001b (17MHz) because the Host Driver use this value...
Page 939 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER MAXIMUM CURRENT CAPABILITIES REGISTER These registers indicate maximum current capability for each voltage. The value is meaningful if Voltage Support is set in the Capabilities register. If this information is supplied by the Host System via another method, all Maximum Current Capabilities register will be 0.
Page 940 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR CONTROL REGISTER 2 This register contains the SD Command Argument. Register Address Description Reset Value CONTROL2_0 0x7C200080 Control register 2 (Channel 0) CONTROL2_1 0x7C300080 Control register 2 (Channel 1) CONTROL2_2 0x7C400080 Control register 2 (Channel 2)
Page 941 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER Power bit in the “PWRCON register”, when being set. ‘0’=No Sync, no switch output enable signal (Command, Data) ‘1’=Sync, control output enable signal (Command, Data) TxBStartEn [11] CE-ATA I/F mode Busy state check before Tx Data start state...
Page 942 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR CONTROL REGISTER 3 REGISTER Register Address Description Reset Value FIFO Interrupt Control (Control Register 3) CONTROL3_0 0x7C200084 0x7F5F3F1F (Channel 0) FIFO Interrupt Control (Control Register 3) CONTROL3_1 0x7C300084 0x7F5F3F1F (Channel 1) FIFO Interrupt Control (Control Register 3)
Page 943 S3C6400X RISC MICROPROCESSOR HSMMC CONTROLLER HOST CONTROLLER VERSION REGISTER This register contains the SD Command Argument. Register Address Description Reset Value HCVER0 0x7C2000FE HWInit Host Controller Version Register (Channel 0) 0x1300 HCVER1 0x7C3000FE HWInit Host Controller Version Register (Channel 1)
Page 944 HSMMC CONTROLLER S3C6400X RISC MICROPROCESSOR Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 27-68 Specifications and information herein are subject to change without notice.
Page 945 S3C6400X RISC MICROPROCESSOR MIPI HSI MIPI HSI INTERFACE CONTROLLER OVERVIEW MIPI HSI interface is a kind of high speed synchronous serial interface. Figure 28-1 MIPI HSI signal definition Block Diagram Figure 28-2 MIPI HSI transmitting example Block Diagram 28-1...
Page 946 MIPI HSI S3C6400X RISC MICROPROCESSOR FEATURES THE MIPI HSI RX/TX CONTROLLER FEATURES: The MIPI HSI interface is a uni-direction interface. MIPI HSI Rx maximum bandwidth is 100Mbps. MIPI HSI TX controller uses PCLK for data transmitting. Tx module: Status register FIFO status (fifo full, fifo empty, fifo write point, fifo read point) MIPI status (internal status : current status &...
Page 947 S3C6400X RISC MICROPROCESSOR MIPI HSI Rx module: Status register FIFO status (fifo full, fifo empty, fifo write point, fifo read point) MIPI status (internal status : current status & next status) Configuration register 0 Operation mode select (stream mode or frame mode)
Page 948 MIPI HSI S3C6400X RISC MICROPROCESSOR BLOCK DIAGRAM TOP-LEVEL BLOCK DIAGRAM Basic architectures of the Rx module part & the Tx module part are similar. Figure 28-3. MIPI HSI interface controller Tx module Top Block Diagram MIPI MRx_ Data APB BUS...
Page 949 S3C6400X RISC MICROPROCESSOR MIPI HSI Tx module part parallel-to-serial block FLAG Flag D == PRE_D? Data PCLK DATA Data Figure 28-5 Parallel -to- Serial block (Tx module Part) Rx module part serial-to-parallel block Figure 28-6 Serial-to-Parallel block (Rx module Part)
Page 950 MIPI HSI S3C6400X RISC MICROPROCESSOR I/O DESCRIPTION TX MODULE I/O LIST Name # bits Function APB Interface Signals (Tx) PCLK APB bus clock PPRESETn APB bus reset PADDR APB bus address PWRITE APB bus write PRDATA APB bus read data...
Page 951 S3C6400X RISC MICROPROCESSOR MIPI HSI RX MODULE I/O LIST Name # bits Function APB Interface Signals (Rx) PCLK APB bus clock PRESETn APB bus reset PADDR APB bus address PWRITE APB bus write PRDATA APB bus read data PWDATA APB bus write data...
Page 952 MIPI HSI S3C6400X RISC MICROPROCESSOR TIMING DIAGRAM WAVEFORM Figure 28-7 Waveform Block Diagram SIGNAL TIMINGS Table 28-3 Signal timings Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 953 S3C6400X RISC MICROPROCESSOR MIPI HSI SINGLE/BURST CHANNEL ID MODE < Stream mode > < Frame mode > Figure 28-8 Example of Burst channel ID mode Block Diagram In the Single channel ID mode, channel ID is attached in front of each data to send. In the Burst channel ID mode, channel ID is attached only in front of the first data frame which is sent after the IDLE state, and then only 32bit data are sent until going into IDLE mode again.
Page 954 MIPI HSI S3C6400X RISC MICROPROCESSOR FRAME MODE Normal mode Figure 28-10 Example of Frame mode (normal mode) Block Diagram Break frame Figure 28-11 Break frame Block Diagram The flag line continues to toggle until the transfer is finished, because the break frame is transferring more than 36 ‘0’s.
Page 955 S3C6400X RISC MICROPROCESSOR MIPI HSI FUNCTIONAL DESCRIPTION MIPI HSI TX CONTROLLER PART Finite State Machine TxBRK state_timeout Break frame trans frame_mode break_done && br_frame Err_clr Error IDLE frame_mode generated && br_frame Tx module sleeping TxIDLE Waiting ready INT_fifo_empty : active...
Page 956 MIPI HSI S3C6400X RISC MICROPROCESSOR MIPI HSI RX CONTROLLER PART Finite State Machine (shift_cnt != expected_dat Error a_cnt) && Receive the generated state_timeout (shift_cnt == other data expected_dat RxReady : inactive Break_error a_cnt) && RxReady : inactive state_timeout State_ Err_clr Frame_mode &...
Page 957 S3C6400X RISC MICROPROCESSOR MIPI HSI SPECIAL FUNCTION REGISTERS REGISTER MAP MIPI HSI Tx Controller Register Map Table Register Address Description Reset Value STATUS_REG 0x7E006000 MIPI HSI Tx controller status register 0x00010000 CONFIG_REG 0x7E006004 MIPI HSI Tx controller configuration register 0xFFFFFF02...
Page 958 MIPI HSI S3C6400X RISC MICROPROCESSOR INDIVIDUAL REGISTER DESCRIPTIONS (TX CONTROLLER) STATUS_REG STATUS_REG is an internal logic monitoring window. Address = BASEADDR (0x7E00_6000) Bits Name Description Reset Value [31] reserved Reserved bit [30:28] next_state Next state* [27] reserved Reserved bit [26:24]...
Page 959 S3C6400X RISC MICROPROCESSOR MIPI HSI Address = BASEADDR + 0x04 (0x7E00_6004) Bits Name Description Reset Value [31:24] TxHOLD time TxHOLD state timer setting value 0xFF [23:16] TxIDLE time TxIDLE state timer setting value 0xFF [15:8] TxREQ time TxREQ state timer setting value...
Page 960 MIPI HSI S3C6400X RISC MICROPROCESSOR Bits Name Description Reset Value Brframe_end Break frame transfer–done in Frame mode (set ‘1’ for clearing) TxFIFO_empty TxFIFO empty interrupt (set ‘1’ for clearing) Table 28-8 INTSRC_REG register description INTMSK_REG INTMSK_REG is interrupt mask & DMA request enabler register.
Page 961 S3C6400X RISC MICROPROCESSOR MIPI HSI Bits Name Description Reset Value [31:1] Reserved Reserved bits 0x00000000 Sw_rst Software reset 0 : set 1 : reset Table 28-10 SWRST_REG register description CHID_REG CHID_REG is used to transfer channel ID. Address = BASEADDR + 0x18 (0x7E00_6018)
Page 962 MIPI HSI S3C6400X RISC MICROPROCESSOR Address = BASEADDR + 0x1C Bits Name Description Reset Value [31:0] TxFIFO in TxFIFO data input for transmitting Table 28-12 DATA_REG register description Note: If willing to transfer data is loaded on TxFIFO, data which is located on FIFO is transferred to the other side’s RX through MIPI HSI Tx controller until TxFIFO is fully empty.
Page 963 S3C6400X RISC MICROPROCESSOR MIPI HSI INDIVIDUAL REGISTER DESCRIPTIONS (RX CONTROLLER) STATUS_REG STATUS_REG is an internal logic monitoring window. Address = BASEADDR Bits Name Description Reset Value [31] Reserved Reserved bit [30:28] Next_state Next state* [27] Reserved Reserved bit [26:24] Curr_state...
Page 964 MIPI HSI S3C6400X RISC MICROPROCESSOR CONFIG0_REG CONFIG0_REG is used to set the configuration of Rx controller. Address = BASEADDR + 0x04 Bits Name Description Reset Value [31:30] Reserved Reserved bits [29:28] DREQ_thres_val DMA request threshold value 0x00 DMA request signal is active when valid data in...
Page 965 S3C6400X RISC MICROPROCESSOR MIPI HSI Address = BASEADDR + 0x08 Bits Name Description Reset Value [31] RxFIFO_clr Break frame receiving timer setting value [30:28] Reserved Reserved bits [27] RxFIFO_timer_e RxFIFO timer enabler [26:24] Reserved Reserved bits [23:0] RxFIFO_time RxFIFO timer setting value...
Page 966 MIPI HSI S3C6400X RISC MICROPROCESSOR INTMSK_REG INTMSK_REG is interrupt mask & DMA reqeust enabler register. Address = BASEADDR + 0x10 Bits Name Description Reset Value [31] DMA_req_en DMA request signal enable 0: enable 1: disable [30:9] Reserved Reserved bits 0x0000000...
Page 967 S3C6400X RISC MICROPROCESSOR MIPI HSI SWRST_REG SWRST_REG is software reset. Address = BASEADDR + 0x14 Bits Name Description Reset Value [31:1] Reserved Reserved bits 0x00000000 Sw_rst Software reset 0 : set 1 : reset Table 28-18 SWRST_REG register description CHID_REG CHID_REG is channel ID RxFIFO output.
Page 968 MIPI HSI S3C6400X RISC MICROPROCESSOR PROGRAMMING GUIDE BASIC DRAWING FUNCTION Tx module programming guide flow chart Start Put the channel ID Put the Data at FIFO Change Channel ID? FIFO full? FIFO empty? Wait FIFO not full Wait FIFO empty Figure 28-14 Basic Tx module programming flow chart Figure 28-17 is programming guide for Tx module’s operation.
Page 969 S3C6400X RISC MICROPROCESSOR MIPI HSI Rx module programming guide flow chart Start Wait interrupt (RxDONE || FIFO full || FIFO time out)? Read channel ID reg. Read Data FIFO FIFO empty ? Figure 28-15 Basic Rx module programming flow chart Figure 28-18 is the basis flow chart that shows how to handle transferred Data in Rx module.
Page 970 S3C6400X RISC MICROPROCESSOR SPI CONTROLLER OVERVIEW The Serial Peripheral Interface (SPI) can interface the serial data transfer. SPI includes two 8, 16, 32-bit shift registers for transmission and receiving, respectively. During SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface.
Page 971 FIFO ACCESS The SPI in S3C6400x supports CPU access and DMA access to FIFOs. Data size of CPU access and DMA access to FIFOs can be selected either from 8-bit or 32-bit data. If 8-bit data size is selected, valid bits are from 0 bit to 7 bit.
Page 972 S3C6400X RISC MICROPROCESSOR SPI CONTROLLER APB BUS clock. When timer value is to be zero, interrupt signal is occurred and CPU can remove trailing bytes in FIFO. PACKET NUMBER CONTROL SPI can control the number of packets to be received in master mode. If there is any number of packets to be received, just set the SFR(Packet_Count_reg) how many packets have to be received.
Page 973 SPI CONTROLLER S3C6400X RISC MICROPROCESSOR SPI TRANSFER FORMAT The S3C6400X supports 4 different formats to transfer the data. Figure 29-1 describes four waveforms for SPICLK.. CPOL = 0, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO *MSB *MSB : MSB of previous frame...
Page 974 S3C6400X RISC MICROPROCESSOR SPI CONTROLLER SPECIAL FUNCTION REGISTER DESCRIPTIONS SETTING SEQUENCE OF SPECIAL FUNCTION REGISTER Special Function Register must be set in the following sequence. (nCS manual mode) 1. Set Transfer Type. ( CPOL & CPHA set ) 2. Set Clock configuration register.
Page 975 SPI CONTROLLER S3C6400X RISC MICROPROCESSOR SPI Tx Channel On TxChOn 1’b0 0: Channel Off 1: Channel On Register Address Description Reset Value Clk_CFG(Ch0) 0x7F00B004 Clock configuration register Clk_CFG(Ch1) 0x7F00C004 Clock configuration register Clk_CFG Description Initial State Clock source selection to generate SPI clock-out...
Page 976 S3C6400X RISC MICROPROCESSOR SPI CONTROLLER reserved [4:3] RxDMA On DMA mode on/off 1’b0 0 : DMA mode off 1 : DMA mode on TxDMA On DMA mode on/off 1’b0 0 : DMA mode off 1 : DMA mode on DMA transfer DMA transfer type, single or 4 bust.
Page 977 SPI CONTROLLER S3C6400X RISC MICROPROCESSOR 0: Disable 1:Enable Interrupt Enable for TxOverrun IntEnTxOverrun 1’b0 0: Disable 1:Enable Interrupt Enable for TxUnderrun. In slave mode, this bit must be clear first after turning on slave TX path. IntEnTxUnderrun 1’b0 0: Disable...
Page 978 S3C6400X RISC MICROPROCESSOR SPI CONTROLLER 0: no error, 1: underrun error 0 : data in FIFO less than trigger level RxFifoRdy 1 : data in FIFO more than trigger level 1’b0 0 : data in FIFO more than trigger level TxFifoRdy 1’b0...
Page 979 SPI CONTROLLER S3C6400X RISC MICROPROCESSOR Register Address Description Reset Value Pending_clr_reg(Ch0) 0x7F00B024 R/W Pending clear register Pending_clr_reg(Ch1) 0x7F00C024 R/W Pending clear register Status_Pending Description Initial State _clear_reg TX underrun pending clear bit TX_underrun_clr 1’b0 0: non-clear 1:clear TX overrun pending clear bit TX_overrun_clr 1’b0...
Page 980 S3C6400X RISC MICROPROCESSOR SPI CONTROLLER Register Address Description Reset Value SWAP_CFG(Ch0) 0x7F00B028 R/W SWAP config register SWAP_CFG (Ch1) 0x7F00C028 R/W SWAP config register SWAP_CFG Description Initial State RX_Half-word 0: off 1: swap 1’b0 swap 0: off 1: swap RX_Byte swap 1’b0...
Page 981 SPI CONTROLLER S3C6400X RISC MICROPROCESSOR Register Address Description Reset Value FB_Clk_sel (Ch0) 0x7F00B02C R/W Feedback clock selecting register. FB_Clk_sel (Ch1) 0x7F00C02C R/W Feedback clock selecting register. SWAP_CFG Description Initial State : no additional delay SPICLKout delay 1’b0 : 2.7ns delay (base on typical)
Page 982 In multi-master IIC-bus mode, multiple S3C6400X RISC microprocessors can receive or transmit serial data to or from slave devices. The master S3C6400X can initiate and terminate a data transfer over the IIC-bus. The IIC-bus in the S3C6400X uses Standard bus arbitration procedure.
Page 983 IIC-BUS INTERFACE S3C6400X RISC MICROPROCESSOR Address Register Comparator IIC-Bus Control Logic IICCON IICSTAT 4-bit Prescaler Shift Register PCLK Shift Register (IICDS) Data Bus Figure 30-1. IIC-Bus Block Diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 984 S3C6400X RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE The S3C6400X IIC-bus interface has four operation modes: — Master transmitter mode — Master receive mode — Slave transmitter mode — Slave receive mode Functional relationships among these operating modes are described below.
Page 985 IIC-BUS INTERFACE S3C6400X RISC MICROPROCESSOR DATA TRANSFER FORMAT Every byte placed on the SDA line must be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition will have the address field. The address field can be transmitted by the master when the IIC-bus is operating in Master mode.
Page 986 S3C6400X RISC MICROPROCESSOR IIC-BUS INTERFACE Clock to Output Data Output by Transmitter Data Output by Receiver SCL from Master Start Condition Clock Pulse for Acknowledgment Figure 30-4. Acknowledge on the IIC-Bus Block Diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 987 When data is received in the Receive mode, the IIC-bus interface will wait until IICDS register is read. Before the new data is read out, the SCL line will be held low and then released after it is read. The S3C6400X holds the interrupt to identify the completion of the new data reception.
Page 988 S3C6400X RISC MICROPROCESSOR IIC-BUS INTERFACE FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1. Write own slave address on IICADD register, if needed. 2. Set IICCON register. a) Enable interrupt b) Define SCL period 3.
Page 989 IIC-BUS INTERFACE S3C6400X RISC MICROPROCESSOR START Master Rx mode has been configured. Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Stop?
Page 990 S3C6400X RISC MICROPROCESSOR IIC-BUS INTERFACE START Slave Tx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? The IIC address match interrupt is generated. Write data to IICDS.
Page 991 IIC-BUS INTERFACE S3C6400X RISC MICROPROCESSOR START Slave Rx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? The IIC address match interrupt is generated. Read data from IICDS.
Page 992 S3C6400X RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE SPECIAL REGISTERS MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER Register Address Description Reset Value IICCON 0x7F004000 IIC-Bus control register 0x0X IICCON Description Initial State IIC-bus acknowledge enable bit. Acknowledge generation 0: Disable 1: Enable In Tx mode, the IICSDA is free in the ack time.
Page 993 IIC-BUS INTERFACE S3C6400X RISC MICROPROCESSOR MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register Address Description Reset Value IICSTAT 0x7F004004 IIC-Bus control/status register IICSTAT Description Initial State Mode selection [7:6] IIC-bus master/slave Tx/Rx mode select bits. 00: Slave receive mode 01: Slave transmit mode...
Page 994 S3C6400X RISC MICROPROCESSOR IIC-BUS INTERFACE MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER Register Address Description Reset Value IICADD 0x7F004008 IIC-Bus address register 0xXX IICADD Description Initial State Slave address [7:0] 7-bit slave address, latched from the IIC-bus. XXXXXXXX When serial output enable = 0 in the IICSTAT, IICADD is write- enabled.
Page 995 IIC-BUS INTERFACE S3C6400X RISC MICROPROCESSOR MULTI-MASTER IIC-BUS LINE CONTROL (IICLC) REGISTER Register Address Description Reset Value IICLC 0x7F004010 IIC-Bus multi-master line control register 0x00 IICLC Description Initial State Filter enable IIC-bus filter enable bit. When SDA port is operating as input, this bit should be High.
Page 996 S3C6400 RISC MICROPROCESSOR UART UART This chapter describes the universal asynchronous receiver/transmitter (UART) serial ports included in the S3C6400 RSIC microprocessor. OVERVIEW The S3C6400 Universal Asynchronous Receiver and Transmitter (UART) provide four independent asynchronous serial I/O (SIO) ports. Each of asynchronous serial I/O (SIO) ports can operate in interrupt-based or DMA-based mode.
Page 997 UART S3C6400 RISC MICROPROCESSOR Peripheral BUS Transmitter Transmit FIFO Register (FIFO mode) Transmit Buffer Register(64 Byte) Transmit Holding Register (Non-FIFO mode) Transmit Shifter TXDn Control Buad-rate Clock Source Unit Generator Receiver Receive Shifter RXDn Receive Holding Register (Non-FIFO mode only) Receive Buffer Register(64 Byte) Receive FIFO Register...
Page 998 S3C6400 RISC MICROPROCESSOR UART DESCRIPTION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, Loopback mode, Infra-red mode, and auto flow control. DATA TRANSMISSION The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn).
Page 999 UART S3C6400 RISC MICROPROCESSOR AUTO FLOW CONTROL(AFC) The S3C6400 UART 0 and UART 1 support auto flow control with nRTS and nCTS signals. In case, it can be connected to external UARTs. If you want to connect a UART to a Modem, you must disable auto flow control bit in UMCONn register and control the signal of nRTS by software.
Page 1000 S3C6400 RISC MICROPROCESSOR UART RS-232C INTERFACE To connect the UART to modem interface (instead of null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals are needed. In this case, you can control these signals with general I/O ports by software because the AFC does not support the RS-232C interface.

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