Samsung S5PC110 Manual page 845

S5PC110_UM
2.5.1.1 Multi-Master I
•
I2CCON0, R/W, Address = 0xE180_0000
•
I2CCON2, R/W, Address = 0xE1A0_0000
•
I2CCON_HDMI_DDC, R/W, Address = 0xFAB0_0000
•
I2CCON_HDMI_PHY, R/W, Address = 0xFA90_0000
I2CCON
Acknowledge generation
(1)
Tx clock source
selection
(5)
Tx/Rx Interrupt
Interrupt pending flag
(2) (3)
(4)
Transmit clock value
NOTE:
1 Interfacing with EEPROM, the ACK generation may be disabled before reading the last data to generate the STOP
condition in Rx mode.
2
2. An I C-bus interrupt occurs if 1) if a 1-byte transmit or receive operation is complete. In other words, ack period is
finished. 2) A general call or a slave address match occurs, 3) Bus arbitration fails.
3. To adjust the setup time of SDA before SCL rising edge, I2CDS has to be written before clearing the I
pending bit.
4. I2CCLK is determined by I2CCON[6].
Tx clock can vary by SCL transition time. If I2CCON[6]=0, I2CCON[3:0]=0x0 or 0x1 is not available.
5. If the I2CCON[5]=0, I2CCON[4] does not operate correctly.
Therefore, It is recommended to set I2CCON[5]=1, even if you do not use the I
2
C-Bus Control Register
Bit
2
[7]
I C-bus acknowledge enable bit.
0 = Disables
1 = Enables
In Tx mode, the I2CSDA is free in the ACK time.
In Rx mode, the I2CSDA is L in the ACK time.
[6] Source clock of I2C-bus transmit clock prescaler selection bit.
0 = I2CCLK = fPCLK /16
1 = I2CCLK = fPCLK /512
2
[5]
I C-Bus Tx/Rx interrupt enable/ disable bit.
0 = Disables
1 = Enables
2
[4]
I C-bus Tx/Rx interrupt pending flag. This bit cannot be written
to 1. If this bit is read as 1, the I2CSCL is tied to L and the I
is stopped. To resume the operation, clear this bit as 0.
0 = 1) No interrupt is pending (If read).
2) Clear pending condition and
Resume the operation (If write).
1 = 1) Interrupt is pending (If read)
2) N/A (If write)
2
[3:0] I
C-Bus transmit clock prescaler.
2
I C-Bus transmit clock frequency is determined by this 4-bit
prescaler value, according to the following formula:
Tx clock = I2CCLK/(I2CCON[3:0]+1).
Description
2
C interrupt.
2 IIC-BUS INTERFACE
Initial State
0
0
0
0
2
C
Undefined
2
C interrupt
2-13