Samsung S5PC110 Manual page 713

S5PC110_UM
Register Address
DA_3 0xFA20_0464
DA_4 0xFA20_0484
DA_5 0xFA20_04A4
DA_6 0xFA20_04C4
DA_7 0xFA20_04E4
Channel Control Registers. For more information, refer to page 3-30 of "PL330 TRM".
CC_0 0xFA20_0408
CC_1 0xFA20_0428
CC_2 0xFA20_0448
CC_3 0xFA20_0468
CC_4 0xFA20_0488
CC_5 0xFA20_04A8
CC_6 0xFA20_04C8
CC_7 0xFA20_04E8
Loop Counter 0 Registers. For more information, refer to page 3-35 of "PL330 TRM".
LC0_0 0xFA20_040C
LC0_1 0xFA20_042C
LC0_2 0xFA20_044C
LC0_3 0xFA20_046C
LC0_4 0xFA20_048C
LC0_5 0xFA20_04AC
LC0_6 0xFA20_04CC
LC0_7 0xFA20_04EC
Loop Counter 1 Registers. For more information, refer to page 3-36 of "PL330 TRM".
LC1_0 0xFA20_0410
LC1_1 0xFA20_0430
LC1_2 0xFA20_0450
LC1_3 0xFA20_0470
LC1_4 0xFA20_0490
LC1_5 0xFA20_04B0
LC1_6 0xFA20_04D0
LC1_7 0xFA20_04F0
Reserved 0xFA20_0414-
0xFA20_041C
R/W
R Specifies the Destination Address for DMA Channel
3.
R Specifies the Destination Address for DMA Channel
4.
R Specifies the Destination Address for DMA Channel
5.
R Specifies the Destination Address for DMA Channel
6.
R Specifies the Destination Address for DMA Channel
7.
R Specifies the Channel Control for DMA Channel 0.
R Specifies the Channel Control for DMA Channel 1.
R Specifies the Channel Control for DMA Channel 2.
R Specifies the Channel Control for DMA Channel 3.
R Specifies the Channel Control for DMA Channel 4.
R Specifies the Channel Control for DMA Channel 5.
R Specifies the Channel Control for DMA Channel 6.
R Specifies the Channel Control for DMA Channel 7.
R Specifies the Loop Counter 0 for DMA Channel 0.
R Specifies the Loop Counter 0 for DMA Channel 1.
R Specifies the Loop Counter 0 for DMA Channel 2.
R Specifies the Loop Counter 0 for DMA Channel 3.
R Specifies the Loop Counter 0 for DMA Channel 4.
R Specifies the Loop Counter 0 for DMA Channel 5.
R Specifies the Loop Counter 0 for DMA Channel 6.
R Specifies the Loop Counter 0 for DMA Channel 7.
R Specifies the Loop Counter 1 for DMA Channel 0.
R Specifies the Loop Counter 1 for DMA Channel 1.
R Specifies the Loop Counter 1 for DMA Channel 2.
R Specifies the Loop Counter 1 for DMA Channel 3.
R Specifies the Loop Counter 1 for DMA Channel 4.
R Specifies the Loop Counter 1 for DMA Channel 5.
R Specifies the Loop Counter 1 for DMA Channel 6.
R Specifies the Loop Counter 1 for DMA Channel 7.
- Reserved
Description
1 DMA CONTROLLER
Reset Value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
-
1-7