Samsung S5PC110 Manual page 326

S5PC110_UM
3.7.3.5 Clock Source Control Registers (CLK_SRC4, R/W, Address = 0xE010_0210)
CLK_SRC4
UART3_SEL
UART2_SEL
UART1_SEL
UART0_SEL
MMC3_SEL
MMC2_SEL
MMC1_SEL
MMC0_SEL
Bit
[31:28] Control MUXUART3, which is the source clock of UART3
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[27:24] Control MUXUART2, which is the source clock of UART2
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[23:20] Control MUXUART1, which is the source clock of UART1
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[19:16] Control MUXUART0, which is the source clock of UART0
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[15:12] Control MUXMMC3, which is the source clock of MMC3
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[11:8] Control MUXMMC2, which is the source clock of MMC2
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[7:4] Control MUXMMC1, which is the source clock of MMC1
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[3:0] Control MUXMMC0, which is the source clock of MMC0
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
Description
3 CLOCK CONTROLLER
Initial State
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
3-29