Samsung S5PC110 Manual page 819

S5PC110_UM
UCONn
Loop-back Mode
Send Break
Signal
Transmit Mode
Receive Mode
NOTE:
1. DIV_VAL = UBRDIVn + (num of 1's in UDIVSLOTn)/16. Refer to 1.6.1.11 UART Channel Baud Rate Division Register and
1.6.1.12 UART Channel Dividing Slot Register
2. S5PC110 use a level-triggered interrupt controller. Therefore, these bits must be set to 1 for every transfer.
3. If the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA
receive mode with FIFO, the Rx interrupt is generated (receive time out). You must check the FIFO status
and read out the rest.
Bit
[5] Setting loop-back bit to 1 trigger the UART to enter the loop-back
mode. This mode is provided for test purposes only.
0 = Normal operation
1 = Loop-back mode
[4] Setting this bit trigger the UART to send a break during 1 frame
time. This bit is automatically cleared after sending the break
signal.
0 = Normal transmit
1 = Sends the break signal
[3:2] Determines which function is able to write Tx data to the UART
transmit buffer register.
00 = Disables
01 = Interrupt request or polling mode
10 = DMA mode
11 = Reserved
[1:0] Determines which function is able to read data from UART
receive buffer register.
00 = Disables
01 = Interrupt request or polling mode
10 = DMA mode
11 = Reserved
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
Description Initial State
0
0
00
00
1-17