Clock Divider Control Register - Samsung S5PC110 Manual

S5PC110_UM

3.7.4 CLOCK DIVIDER CONTROL REGISTER

S5PC110 has several clock dividers to support various operating clock frequency. The clock divider ratio can be
controlled by CLK_DIV0, CLK_DIV1, 2, 3, 4, and 5.
There are operating frequency limitations. The maximum operating frequency of SCLKAPLL, SCLKMPLL,
SCLKA2M, HCLK_MSYS, and PCLK_MSYS are 800 MHz, 667 MHz, 400 MHz, 200 MHz, and 100 MHz,
respectively. These operating clock conditions must be met through CLK_DIVX configuration.
Divider for internal memory shown as DIV
control registers since the divider value is fixed to two.
Whenever clock divider control register is changed, it is recommended to check clock divider status registers
before using the new clock output. This guarantees corresponding divider finishes changing to a new dividing
value before it's output is used by other modules.
3.7.4.1 Clock Divider Control Register (CLK_DIV0, R/W, Address = 0xE010_0300)
CLK_DIV0
Reserved
PCLK_PSYS_RATIO
HCLK_PSYS_RATIO
Reserved
PCLK_DSYS_RATIO
HCLK_DSYS_RATIO
Reserved
PCLK_MSYS_RATIO
Reserved
HCLK_MSYS_RATIO
Reserved
A2M_RATIO
Reserved
APLL_RATIO
in
IMEM
Bit
[31] Reserved
[30:28] DIVPCLKP clock divider ratio,
PCLK_PSYS = HCLK_PSYS / (PCLK_PSYS_RATIO + 1)
[27:24] DIVHCLKP clock divider ratio,
HCLK_PSYS = MOUT_PSYS / (HCLK_PSYS_RATIO + 1)
[23] Reserved
[22:20] DIVPCLKD clock divider ratio,
PCLK_DSYS = HCLK_DSYS / (PCLK_DSYS_RATIO + 1)
[19:16] DIVHCLKD clock divider ratio,
HCLK_DSYS = MOUT_DSYS / (HCLK_DSYS_RATIO + 1)
[15] Reserved
[14:12] DIVPCLKM clock divider ratio,
PCLK_MSYS = HCLK_MSYS / (PCLK_MSYS_RATIO + 1)
[11] Reserved
[10:8] DIVHCLKM clock divider ratio,
HCLK_MSYS = ARMCLK / (HCLK_MSYS_RATIO + 1)
[7] Reserved
[6:4] DIVA2M clock divider ratio,
SCLKA2M = SCLKAPLL / (A2M_RATIO + 1)
[3] Reserved
[2:0] DIVAPLL clock divider ratio,
ARMCLK = MOUT_MSYS / (APLL_RATIO + 1)
does not have corresponding fields in clock divider
Figure 3-3
Description
3 CLOCK CONTROLLER
Initial State
0
0x0
0x0
0
0x0
0x0
0
0x0
0
0x0
0
0x0
0
0x0
3-34