Samsung S5PC110 Manual page 961

S5PC110_UM
5.8.7.16 Device Endpoint-n Interrupt Register (DIEPINTn/DOEPINTn, R/W, Address = 0xEC00_0908 +n*20h,
0xEC00_0B08 +n*20h)
Endpoint_number: 0 ≤ n ≤ 15
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application
must read this register if the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
is set. Before the application reads this register, it must first read the Device All Endpoints Interrupt (DAINT)
register to get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear
the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
DIEPINTn/ Bit
DOEPINTn
EPEna [31:15]
NYETIntrpt [14]
NAKIntrpt [13]
BbleErrIntrpt [12]
Packet Dropped [11]
Status
Reserved [10]
BNAIntr [9]
TxfifoUndrn [8]
OutPktErr
Reserved
NYET interrupt (NYETIntrpt) The core generates this
interrupt when a NYET response is transmitted for a non
isochronous OUT endpoint.
NAK interrupt (NAKIntrpt) The core generates this interrupt
when a NAK is transmitted or received by the device. In
case of isochronous IN endpoints the interrupt gets
generated when a zero length packet is transmitted due to
un-availability of data in the TXFifo.
BbleErr (Babble Error) interrupt (BbleErrIntrpt) The core
generates this interrupt when babble is received for the
endpoint.
PktDrpSts (Packet Dropped Status) This bit indicates to the
application that an ISOC OUT packet has been dropped.
This bit does not have an associated mask bit and does not
generate an interrupt. Dependency: This bit is valid in non
Scatter/Gather DMA mode when periodic transfer interrupt
feature is selected.
-
Buffer Not Available Interrupt
This bit is valid only when Scatter/Gather DMA mode is
enabled. The core generates this interrupt when the
descriptor accessed is not ready for the Core to process,
such as Host busy or DMA done
Fifo Underrun
Applies to IN endpoints Only This bit is valid only when
thresholding is enabled.
The core generates this interrupt when it detects a transmit
FIFO underrun condition for this endpoint.
OUT Packet Error
Applies to OUT endpoints Only This interrupt is valid only
when thresholding is enabled.
This interrupt is asserted when the core detects an overflow
or a CRC error for non-Isochronous OUT packet.
Description
5 USB2.0 HS OTG
R/W Initial State
- 17'h0
R_SS 1'b0
_WC
R_SS 1'b0
_WC
R_SS 1'b0
_WC
R_SS 1'b0
_WC
- -
R_SS
_WC
R_SS 1'b0
_WC
5-85