Miscellaneous Sfrs - Samsung S5PC110 Manual

Risc microprocessor
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S5PC110_UM

3.7.11 MISCELLANEOUS SFRS

3.7.11.1 Miscellaneous SFRs (DISPLAY_CONTROL, R/W, Address = 0xE010_7008)
DISPLAY_CONTROL
Reserved
DISPLAY_PATH_SEL
3.7.11.2 Miscellaneous SFRs (AUDIO_ENDIAN, R/W, Address = 0xE010_700C)
AUDIO_ENDIAN
Reserved
RP_R_ENDIAN
RP_W_ENDIAN
ARM_R_ENDIAN
ARM_W_ENDIAN
Bit
[31:2]
Reserved
[1:0]
Display path selection
00: RGB=--- I80=FIMD ITU=FIMD
01: RGB=--- I80=--- ITU=FIMD
10: RGB=FIMD I80=FIMD ITU=FIMD
11: RGB=FIMD I80=FIMD ITU=FIMD
Bit
[31:4]
Reserved
[3]
Endian selection for RP read channel
(0: little endian, 1: big endian)
[2]
Endian selection for RP write channel channel
(0: little endian, 1: big endian)
[1]
Endian selection for ARM read channel channel
(0: little endian, 1: big endian)
[0]
Endian selection for ARM write channel channel
(0: little endian, 1: big endian)
Description
Description
3 CLOCK CONTROLLER
Initial State
0x0000_0000
0
Initial State
0x0000_0000
0
0
0
0
3-63

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