Samsung S5PC110 Manual page 561

S5PC110_UM 1 DRAM CONTROLLER
Figure 1-10 Timing Diagram of Read Data Capture
(LPDDR/LPDDR2, low frequency, RL=3, rd_fetch=0)
tDQSCK + Delay is relatively small compared to the clock period during low frequencies as shown in
Figure 1-10.
In this situation, negedge sampling happens before read latency and therefore read fetch is set to zero.
To calculate the LPDDR/LPDDR2 rd_fetch value:
rd_fetch (LPDDR/LPDDR2) = INT((-1 + Delay + 0.5T + 0.25T)/T) = INT(Delay/T - 0.25),
Delay: board delay + PHY input delay, T: clock period, INT(x): the rounded-up integer value of x
Therefore, if the value of Delay/T is less than 0.25, rd_fetch is set to zero
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