Samsung S5PC110 Manual page 347

S5PC110_UM
3.7.5.9 Clock Gating Exceptions
Some clock gating cells have exceptional conditions for gating clocks. This section summarizes this.
SCLK_AUDIO0 is gated when all of the following register fields are cleared to LOW. This guarantees
SCLK_AUDIO0 is running when any of the load is running.
•
CLK_GATE_IP3[0] for SPDIF
•
CLK_GATE_IP3[4] for I2S0
•
CLK_GATE_IP3[28] for PCM0
SCLK_AUDIO1 is gated when all of the following register fields are cleared to LOW. This guarantees
SCLK_AUDIO1 is running when any of the load is running.
•
CLK_GATE_IP3[0] for SPDIF
•
CLK_GATE_IP3[5] for I2S1
•
CLK_GATE_IP3[29] for PCM1
SCLK_AUDIO2 is gated when all of the following register fields are cleared to LOW. This guarantees
SCLK_AUDIO2 is running when any of the load is running.
•
CLK_GATE_IP3[0] for SPDIF
•
CLK_GATE_IP3[6] for I2S2
•
CLK_GATE_IP3[30] for PCM2
3 CLOCK CONTROLLER
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