Samsung S5PC110 Manual page 327

S5PC110_UM
3.7.3.6 Clock Source Control Registers (CLK_SRC5, R/W, Address = 0xE010_0214)
CLK_SRC5
Reserved
PWM_SEL
Reserved
SPI1_SEL
SPI0_SEL
Bit
[31:16] Reserved
[15:12] Control MUXPWM, which is the source clock of PWM
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[11:8] Reserved
[7:4] Control MUXSPI1, which is the source clock of SPI1
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[3:0] Control MUXSPI0, which is the source clock of SPI0
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
Description
3 CLOCK CONTROLLER
Initial State
0x0
0x0
0x0
0x0
0x0
3-30