Samsung S5PC110 Manual page 798

7.4.5 SD Bus Power Control Sequence .................................................................................................... 7-7
7.4.6 Change Bus Width Sequence .......................................................................................................... 7-8
7.4.7 Timeout Setting for DAT Line ........................................................................................................... 7-9
7.4.8 SD Transaction Generation ............................................................................................................ 7-10
7.4.9 SD Command Issue Sequence ...................................................................................................... 7-11
7.4.10 Command Complete Sequence ................................................................................................... 7-13
7.4.11 Transaction Control with Data Transfer Using DAT Line ............................................................. 7-15
7.4.12 Sequence Without Using DMA ..................................................................................................... 7-16
7.4.13 Sequence Using DMA .................................................................................................................. 7-18
7.5 Abort Transaction................................................................................................................................... 7-20
7.6 DMA Transaction ................................................................................................................................... 7-21
7.7 ADMA (ADvanced dma)......................................................................................................................... 7-22
7.7.1 Block Diagram of ADMA................................................................................................................. 7-22
7.7.2 Example of ADMA Programming.................................................................................................... 7-23
7.7.3 Data Address and Data Length Requirements............................................................................... 7-23
7.7.4 Descriptor Table ............................................................................................................................. 7-24
7.7.5 ADMA States .................................................................................................................................. 7-25
7.8 I/O Description ....................................................................................................................................... 7-27
7.9 Register Description............................................................................................................................... 7-29
7.9.1 Register Map .................................................................................................................................. 7-29
7.9.2 SDMA System Address Register.................................................................................................... 7-34
7.9.3 Block Size Register......................................................................................................................... 7-35
7.9.4 Block Count Register ...................................................................................................................... 7-36
7.9.5 Argument Register.......................................................................................................................... 7-37
7.9.6 Transfer Mode Register.................................................................................................................. 7-38
7.9.7 Command Register......................................................................................................................... 7-41
7.10 Response Register .............................................................................................................................. 7-44
7.10.1 Response Bit Definition for Each Response Type ....................................................................... 7-45
7.10.2 Buffer Data Port Register ............................................................................................................. 7-46
7.10.3 Present State Register ................................................................................................................. 7-47
7.10.4 Host Control Register ................................................................................................................... 7-53
7.10.5 Power Control Register ................................................................................................................ 7-54
7.10.6 Block Gap Control Register .......................................................................................................... 7-55
7.10.7 Wakeup Control Register ............................................................................................................. 7-57
7.10.8 Clock Control Register.................................................................................................................. 7-58
7.10.9 Timeout Control Register.............................................................................................................. 7-60
7.10.10 Software Reset Register............................................................................................................. 7-61
7.10.11 Normal Interrupt Status Register ................................................................................................ 7-63
7.10.12 Error Interrupt Status Register.................................................................................................... 7-67
7.10.13 Normal Interrupt Status Enable Register.................................................................................... 7-70
7.10.14 Error Interrupt Status Enable Register ....................................................................................... 7-72
7.10.15 Normal Interrupt Signal Enable Register.................................................................................... 7-73
7.10.16 Error Interrupt Signal Enable Register ....................................................................................... 7-75
7.10.17 Autocmd12 Error Status Register............................................................................................... 7-77
7.10.18 Capabilities Register................................................................................................................... 7-79
7.10.19 Maximum Current Capabilities Register..................................................................................... 7-81
7.10.20 Force Event Register for Auto CMD12 Error Status................................................................... 7-82
7.10.21 Force Event Register for Error Interrupt Status.......................................................................... 7-83
7.10.22 ADMA Error Status Register....................................................................................................... 7-85
7.10.23 ADMA System Address Register................................................................................................ 7-87
7.10.24 Control Register 2....................................................................................................................... 7-88
7.10.25 Control Registers 3 Register ...................................................................................................... 7-91
7.10.26 Control Register 4....................................................................................................................... 7-92