Samsung S5PC110 Manual page 728

S5PC110_UM
1.2.1.9 Configuration Register0 for DMA_mem (CR0, R, Address = 0xFA20_0E00)
CR0
num_events
num_periph_req
num_chnls
mgr_ns_at_rst
boot_en
periph_req
1.2.1.10 Configuration Register1 for DMA_MEM (CR1, R, Address = 0xFA20_0E04)
CR1
num_i-cache_lines
i-cache_len
* PL330 contains a built-in instruction cache controller.
Bit
[21:17] Specifies the number of interrupt outputs that the DMAC
provides.
b11111 = 32 interrupt outputs, irq[31:0]
[16:12] Specifies the number of peripheral request interfaces that the
DMAC provides.
b00001 = 2 peripheral request interfaces
[6:4] Specifies the number of DMA channels that the DMAC
supports.
b111 = 8 DMA channels
[2] Indicates the status of boot_manager_ns signal when the
DMAC exits from reset.
0 = boot_manager_ns is set to LOW
[1] Indicates the status of boot_from_pc signal when the DMAC
exits from reset.
0 = boot_from_pc is set to LOW
[0] Supports peripheral requests.
1 = DMAC provides the number of peripheral request
interfaces that num_periph_req field specifies.
Bit
[7:4] Specifies the number of i-cache lines.
b0111 = 8 i-cache lines.
[2:0] Specifies the length of an i-cache line.
b101 = 32 bytese
Description
Description
1 DMA CONTROLLER
Initial State
0x1F
0x1
7
0
0
1
Initial State
0x7
0x5
1-22