Samsung S5PC110 Manual page 963

S5PC110_UM
DIEPINTn/ Bit
DOEPINTn
OUTTknEPdis
TimeOUT [3]
SetUp
AHBErr [2]
EPDisbld [1]
XferCompl [0]
OUT Token Received When Endpoint Disabled
Applies only to control OUT endpoints. Indicates that an
OUT token was received when the endpoint was not yet
enabled. This interrupt is asserted on the endpoint for which
the OUT token was received.
Timeout Condition
In dedicated FIFO mode, applies only to Control IN
•
endpoints.
In Scatter/Gather DMA mode, the TimeOUT interrupt is not
•
asserted.
Indicates that the core has detected a timeout condition on
the USB for the last IN token on this endpoint.
SETUP Phase Done
Applies to control OUT endpoints only. Indicates that the
SETUP phase for the control endpoint is complete and no
more back-to-back SETUP packets were received for the
current control transfer. On this interrupt, the application can
decode the received SETUP data packet.
AHB Error
Applies to IN and OUT endpoints.
This is generated only in Internal DMA mode if there is an
AHB error during an AHB read/write. The application reads
the corresponding endpoint DMA address register to get the
error address.
Endpoint Disabled Interrupt
Applies to IN and OUT endpoints.
This bit indicates that the endpoint is disabled per the
application's request.
Transfer Completed Interrupt (XferCompl) Applies to IN and
OUT endpoints.
When Scatter/Gather DMA mode is enabled
•
For IN endpoint this field indicates that the requested data
•
from the descriptor is moved from external system memory
to internal FIFO.
For OUT endpoint this field indicates that the requested
•
data from the internal FIFO is moved to external system
memory. This interrupt is generated only when the
corresponding endpoint descriptor is closed, and the IOC bit
for the corresponding descriptor is set.
When Scatter/Gather DMA mode is disabled, this field
•
indicates that the programmed transfer is complete on the
AHB as well as on the USB, for this endpoint.
Description
5 USB2.0 HS OTG
R/W Initial State
R_SS 1'b0
_WC
-
R_SS 1'b0
_WC
R_SS 1'b0
_WC
R_SS 1'b0
_WC
5-87