Clock Gating Control Register - Samsung S5PC110 Manual

S5PC110_UM

3.7.5 CLOCK GATING CONTROL REGISTER

There are two types of clock gating control registers for disable/enable operation, namely:
•
Clock gating control register by block
•
Clock gating register for by IP
The above two registers are ANDed together to generate a final clock gating enable signal. As a result, if either of
the two register field is turned OFF, the resulting clock is stopped.
3.7.5.1 Clock Gating Control Register (CLK_GATE_SCLK, R/W, Address = 0xE010_0444)
CLK_GATE_SCLK
Reserved
SCLK_FIMC_LCLK
Reserved
3.7.5.2 Clock Gating Control Register (CLK_GATE_IP0, R/W, Address = 0xE010_0460)
CLK_GATE_IP0
CLK_CSIS
Reserved
CLK_ROTATOR
CLK_JPEG
Reserved
CLK_FIMC2
CLK_FIMC1
CLK_FIMC0
Reserved
CLK_MFC
Reserved
CLK_G2D
Bit
[31:6] Reserved
[5] Gating special clock for FIMC local clock
(0: mask, 1: pass)
[4:0] Should be one for all bit
Bit
[31] Gating all clocks for CSIS
[30] Reserved
[29] Gating all clocks for ROTATOR
(0: mask, 1: pass)
[28] Gating all clocks for JPEG
(0: mask, 1: pass)
[27] Reserved
[26] Gating all clocks for FIMC2
(0: mask, 1: pass)
[25] Gating all clocks for FIMC1
(0: mask, 1: pass)
[24] Gating all clocks for FIMC0
(0: mask, 1: pass)
[23:17] Reserved
[16] Gating all clocks for MFC
(0: mask, 1: pass)
[15:13] Reserved
[12] Gating all clocks for G2D
Description
Description
3 CLOCK CONTROLLER
Gated Clock Name
Reserved
SCLK_FIMC_LCLK
Reserved
Gated Clock Name
PCLK_CSIS
SCLK_CSIS
Reserved
ACLK_ROTATOR
ACLK_JPEG
Reserved
ACLK_FIMC2
SCLK_FIMC_LCLK
SCLK_CAM0, 1
ACLK_FIMC1
SCLK_CAM0, 1
ACLK_FIMC0
SCLK_CAM0, 1
Reserved
PCLK_MFC
SCLK_MFC
Reserved
ACLK_G2D
SCLK_G2D
Initial State
0x3FF_FFFF
1
0x1F
Initial State
1
1
1
1
1
1
1
1
0x7F
1
0x7
0x1
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