Samsung S5PC110 Manual page 665

S5PC110_UM
4.5.2.13 ECC0/1 Error Status Register (NFECCERR1, R, Address = 0xB0E0_0030)
•
When ECC Type is 4-bit ECC
NFECCERR1
Reserved [31:26]
MLCErrLocation4 [25:16]
Reserved [15:10]
MLCErrLocation3
NOTE: These values are updated when ECCDecodeDone (NFSTAT[6]) is set ('1').
4.5.2.14 Main data area ECC0 status Register (NFMECC0, R, Address = 0xE810_0034)
•
When ECCType is 1-bit ECC.
NFMECC0
MECC3 [31:24]
MECC2 [23:16]
MECC1 [15:8]
MECC0 [7:0]
NOTE: The NAND flash controller generate NFMECC0/1 when read or write main area data while the
MainECCLock(NFCONT[7]) bit is '0'(Unlock).
•
When ECCType is 4-bit ECC
NFMECC0
4th Parity [31:24]
3rd Parity [23:16]
2nd Parity [15:8]
1st Parity [7:0]
NOTE: The NAND flash controller generate these ECC parity codes when write main area data while the MainECCLock
(NFCON[7]) bit is '0'(unlock).
Bit
Reserved
Error byte location of 4
Reserved
[9:0]
Error byte location of 3
Bit
ECC3 for data
ECC2 for data
ECC1 for data
ECC0 for data
Bit
4th Check Parity generated from main area (512-byte)
3rd Check Parity generated from main area (512-byte)
2nd Check Parity generated from main area (512-byte)
1st Check Parity generated from main area (512-byte)
Description
th
bit error
rd
bit error
Description
Description
4 NAND FLASH CONTROLLER
Initial State
0x00
0x00
0x00
0x000
Initial State
0xFF
0xFF
0xFF
0xFF
Initial State
0x00
0x00
0x00
0x00
4-24