Samsung S5PC110 Manual page 598

S5PC110_UM
2.4.1.1 SROM Bus Width & Wait Control Register (SROM_BW, R/W, Address = 0x0000_0000)
SROM_BW
Reserved [31:24]
ByteEnable5
WaitEnable5
AddrMode5
DataWidth5
ByteEnable4
WaitEnable4
AddrMode4
DataWidth4
ByteEnable3
WaitEnable3
AddrMode3
Bit
Reserved
[23] nWBE / nBE(for UB/LB) control for Memory Bank5
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
[22] Wait enable control for Memory Bank5
0 = Disables WAIT
1 = Enables WAIT
[21] Select SROM ADDR Base for Memory Bank5
0 = SROM_ADDR is Half-word base address.
(SROM_ADDR[22:0] <= HADDR[23:1])
1 = SROM_ADDR is byte base address
(SROM_ADDR[22:0] <= HADDR[22:0])
Note: When DataWidth5 is "0", SROM_ADDR is byte base
address. (Ignored this bit.)
[20] Data bus width control for Memory Bank5
0 = 8-bit
1 = 16-bit
[19] nWBE / nBE(for UB/LB) control for Memory Bank4
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
[18] Wait enable control for Memory Bank4
0 = Disables WAIT
1 = Enables WAIT
[17] Select SROM ADDR Base for Memory Bank4
0= SROM_ADDR is Half-word base address.
(SROM_ADDR[22:0] <= HADDR[23:1])
1= SROM_ADDR is byte base address
(SROM_ADDR[22:0] <= HADDR[22:0])
Note: When DataWidth4 is "0", SROM_ADDR is byte base
address. (Ignored this bit.)
[16] Data bus width control for Memory Bank4
0 = 8-bit
1 = 16-bit
[15] nWBE / nBE(for UB/LB) control for Memory Bank3
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
[14] Wait enable control for Memory Bank3
0 = Disables WAIT
1 = Enables WAIT
[13] Select SROM ADDR Base for Memory Bank3
0 = SROM_ADDR is Half-word base address.
(SROM_ADDR[22:0] <= HADDR[23:1])
Description
2 SROM CONTROLLER
Initial State
0
0
0
0
0
0
0
0
0
0
0
0
2-6