Samsung S5PC110 Manual page 864

S5PC110_UM
3.4.2.10 Status Pending Clear Register
•
PENDING_CLR_REG0, R/W, Address = 0xE130_0024
•
PENDING_CLR_REG1, R/W, Address = 0xE140_0024
PENDING_CLR_REGn
TX_UNDERRUN_CLR
TX_OVERRUN_CLR
RX_UNDERRUN_CLR
RX_OVERRUN_CLR
TRAILING_CLR
NOTE: After error interrupt pending clear, SPI controller should be reset.
Error interrupt list: Tx underrun, Tx overrun, Rx underrun, Rx overrun
Bit
[4] TX underrun pending clear bit
0 = Non-Clear
1 = Clear
[3] TX overrun pending clear bit
0 = Non-Clear
1 = Clear
[2] RX underrun pending clear bit
0 = Non-clear
1 = Clear
[1] RX overrun pending clear bit
0 = Non-Clear
1 = Clear
[0] Trailing pending clear bit
0 = Non-Clear
1 = Clear
3 SERIAL PERIPHERAL INTERFACE
Description Initial State
0
0
0
0
0
3-16